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AS7C3256L-20PC PDF预览

AS7C3256L-20PC

更新时间: 2024-11-01 20:26:11
品牌 Logo 应用领域
ALSC 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 219K
描述
Standard SRAM, 32KX8, 20ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28

AS7C3256L-20PC 数据手册

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High Performance  
32K×8 3.3V  
AS7C3256  
AS7C3256L  
CMOS SRAM  
®
Low voltage 32K×8 CMOS SRAM  
Features  
• Equal access and cycle times  
• Organization: 32,768 words × 8 bits  
• Single 3.3 ± 0.3V power supply  
• 5V tolerant I/O specification  
• High speed  
- 10/12/15/20 ns address access time  
- 3/3/4/5 ns output enable access time  
• Very low power consumption  
- Active: 216 mW max, 10 ns cycle  
- Standby:3.6 mW max, CMOS I/O  
1.1 mW max, CMOS I/O, L version  
• 2.0V data retention  
• Easy memory expansion with CE and OE inputs  
• TTL-compatible, three-state I/O  
• Ideal for cache, modem, portable computing  
- 75% power reduction during CPU idle mode  
• 28-pin JEDEC standard packages  
- 300 mil PDIP and SOJ  
- 8 × 13.4 TSOP  
• ESD protection 2000 volts  
• Latch-up current 200 mA  
Logic block diagram  
Pin arrangement  
TSOP 8×13.4  
DIP, SOJ  
Vcc  
GND  
Input buffer  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
2
3
4
5
6
7
8
28  
Vcc  
WE  
A13  
A8  
A9  
A11  
OE  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
A0  
A1  
A2  
A3  
A4  
A5  
I/O7  
I/O0  
256×128×8  
ARRAY  
A10  
CE  
(262,144)  
9
A6  
A14  
A0  
10  
11  
12  
13  
14  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
I/O0  
I/O1  
I/O2  
GND  
17  
16  
15  
WE  
OE  
CE  
Column decoder  
Control  
circuit  
A
7
A
8
A
9
A A A A  
10 11 12 13  
Selection guide  
7C3256-10  
7C3256-12  
7C3256-15  
7C3256-20  
Unit  
Maximum address access time  
Maximum output enable access time  
Maximum operating current  
10  
3
12  
3
15  
4
20  
5
ns  
ns  
60  
1.0  
0.3  
55  
1.0  
0.3  
50  
1.0  
0.3  
45  
1.0  
0.3  
mA  
mA  
mA  
Maximum CMOS standby current  
L
Shaded areas contain advance information.  
ALLIANCE SEMICONDUCTOR  

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