Datasheet > 存储 > SRAM> AS7C3256A-15TC

AS7C3256A-15TC

更新时间： 2024-10-31 22:56:35

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
9页	248K
描述
3.3V 32K X 8 CMOS SRAM (Common I/O)

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中文翻译

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数据手册

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AS7C3256A-15TC 数据手册

April 2004

AS7C3256A

3.3V 32K X 8 CMOS SRAM (Common I/O)

Features

• TTL-compatible, three-state I/O

• 28-pin JEDEC standard packages

- 300 mil SOJ

- 8 × 13.4 mm TSOP 1

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

• Pin compatible with AS7C3256

• Industrial and commercial temperature options

• Organization: 32,768 words × 8 bits

• High speed

- 10/12/15/20 ns address access time

- 5, 6, 7, 8 ns output enable access time

• Very low power consumption: ACTIVE

- 180mW max @ 10 ns

• Very low power consumption: STANDBY

- 7.2 mW max CMOS I/O

• Easy memory expansion with CE and OE inputs

Logic block diagram

Pin arrangement

28-pin TSOP 1 (8×13.4 mm)

28-pin SOJ (300 mil)

GND

Input buffer

A14

A12

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

I/O7

I/O0

A13

256 X 128 X 8

Array

A14

A12

AS7C3256A

A10

(262,144)

I/O7

I/O6

I/O5

I/O4

I/O3

I/O0

I/O1

I/O2

GND

Column decoder

Control

circuit

A A A A A

10 11 12 13 14

Selection guide

-10

-12

-15

-20

Unit

Maximum address access time

Maximum output enable access time

Maximum operating current

Maximum CMOS standby current

4/23/04; v.2.0

Alliance Semiconductor

P. 1 of 9

12 3 4 5 6 7...9

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AS7C3256A-20JI	ALSC	获取价格	3.3V 32K X 8 CMOS SRAM (Common I/O)
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AS7C3256A-20TC	ALSC	获取价格	3.3V 32K X 8 CMOS SRAM (Common I/O)
AS7C3256A-20TCN	ALSC	获取价格	3.3V 32K X 8 CMOS SRAM (Common I/O)
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