Datasheet > 存储 > SRAM> AS7C32096A-12TCN

AS7C32096A-12TCN

更新时间： 2024-10-01 22:56:35

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器光电二极管 ISM频段
页数	文件大小	规格书
9页	195K
描述
3.3V 256K x 8 CMOS SRAM

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数据手册

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AS7C32096A-12TCN 数据手册

February 2005

Preliminary Information

AS7C32096A

3.3V 256K × 8 CMOS SRAM

Features

• Equal access and cycle times

• Industrial and commercial temperature

• Organization: 262,144 words × 8 bits

• Center power and ground pins

• High speed

- 10/12/15/20 ns address access time

- 4/5/6/7 ns output enable access time

• Low power consumption: ACTIVE

- 650 mW / max @ 10 ns

• Easy memory expansion with CE

• TTL-compatible, three-state I/O

• JEDEC standard packages

- 44-pin TSOP 2

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

OE inputs

• Low power consumption: STANDBY

- 28.8 mW / max CMOS

Logic block diagram

Pin arrangements

44-pin TSOP 2

V_CC

A17

GND

Input buffer

A16

A15

A14

I/O1

I/O8

262,144 × 8

I/O1

I/O2

V_CC

I/O8

I/O7

Array

(2,097,152)

GND

V_CC

GND

I/O3

I/O4

I/O6

I/O5

A13

A12

A11

A10

Column decoder

Control

Circuit

Selection guide

–10

–12

–15

–20

Unit

Maximum address access time

Maximum output enable access time

Industrial

180

170

160

150

140

130

110

100

Maximum operating current

Commercial

Maximum CMOS standby current

2/24/05, v. 1.0

Alliance Semiconductor

P. 1 of 9

12 3 4 5 6 7...9

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