Datasheet > AS7C31026C

AS7C31026C

更新时间： 2024-09-28 04:49:43

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
10页	171K
描述
3.3 V 64K X 16 CMOS SRAM

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中文翻译

获取价格

数据手册

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AS7C31026C 数据手册

September 2006

AS7C31026C

Advance Information

3.3 V 64K X 16 CMOS SRAM

Features

• Industrial (-40^oto 85^oC) temperature

• Organization: 65,536 words × 16 bits

• Center power and ground pins for low noise

• High speed

• JEDEC standard packaging

- 44-pin 400 mil SOJ

- 44-pin TSOP 2-400

- 48-ball 6 × 8 mm BGA

• ESD protection ≥ 2000 volts

- 10 ns address access time

- 5 ns output enable access time

• Low power consumption via chip deselect

• Upper and Lower byte pin

• Easy memory expansion with CE, OE inputs

• TTL-compatible, three-state I/O

Logic block diagram

Pin arrangement

44-Pin SOJ (400 mil), TSOP 2

V_CC

65,536 × 16

Array

GND

I/O15

I/O14

I/O13

I/O12

GND

V_CC

I/O11

I/O10

I/O9

I/O8

A10

A11

I/O0

I/O1

I/O2

I/O3

V_CC

GND

I/O4

I/O5

I/O6

I/O7

A15

A14

A13

A12

I/O0–I/O7

I/O8–I/O15

I/O

buffer

Control circuit

Address decoder

0000048 - BGA Ball-Grid-Array Package

A₀

A₁A₂

I/O8 UB A3

I/O9 I/O10 A5

V_SSI/O11 NC

A4 CE I/O0

A6 I/O1 I/O2

A7 I/O3 V_DD

V_DDI/O12 NC NC I/O4 V_SS

I/O14 I/O13 A14 A15 I/O5 I/O6

I/O15 NC A12 A13 WE I/O7

A9 A10 A11 NC

9/20/06, v 1.0

Alliance Memory

P. 1 of 10

12 3 4 5 6 7...10

中文翻译

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