Datasheet > 存储 > SRAM> AS7C31025B-20JIN

AS7C31025B-20JIN

更新时间： 2024-10-25 22:56:35

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
9页	99K
描述
3.3V 128K X 8 CMOS SRAM (Center power and ground)

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数据手册

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AS7C31025B-20JIN 数据手册

March 2004

AS7C31025B

3.3V 128K X 8 CMOS SRAM (Center power and ground)

Features

• Industrial and commercial temperatures

• Organization: 131,072 x 8 bits

• High speed

- 10/12/15/20 ns address access time

- 5, 6, 7, 8 ns output enable access time

• Low power consumption: ACTIVE

- 252 mW / max @ 10 ns

• Easy memory expansion with CE

• Center power and ground

• TTL/LVTTL-compatible, three-state I/O

• JEDEC-standard packages

- 32-pin, 300 mil SOJ

- 32-pin, 400 mil SOJ

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

, OE inputs

• Low power consumption: STANDBY

- 18 mW / max CMOS

• 6 T 0.18 u CMOS technology

Pin arrangement

Logic block diagram

32-pin SOJ (300 mil)

32-pin SOJ (400 mil)

GND

Input buffer

A16

A15

A14

A13

I/O7

I/O0

I/O1

I/O7

I/O0

512 x 256 x 8

Array

(1,048,576)

I/O6

GND

I/O2

I/O3

I/O5

I/O4

A12

A11

A10

Control

circuit

Column decoder

Selection guide

-10

-12

-15

-20

Unit

Maximum address access time

Maximum output enable access time

Maximum operating current

Maximum CMOS standby current

3/24/04, v. 1.3

Alliance Semiconductor

P. 1 of 9

12 3 4 5 6 7...9

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