Datasheet > 存储 > SRAM> AS7C31024B-10JCN

AS7C31024B-10JCN

更新时间： 2024-11-23 22:56:35

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
9页	121K
描述
3.3V 128K X 8 CMOS SRAM

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中文翻译

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数据手册

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AS7C31024B-10JCN 数据手册

March 2004

AS7C31024B

3.3V 128K X 8 CMOS SRAM

Features

• Industrial and commercial temperatures

• Organization: 131,072 words x 8 bits

• High speed

- 10/12/15/20 ns address access time

- 5, 6, 7, 8 ns output enable access time

• Low power consumption: ACTIVE

- 252 mW / max @ 10 ns

• Easy memory expansion with CE1, CE2, OE inputs

• TTL/LVTTL-compatible, three-state I/O

• 32-pin JEDEC standard packages

- 300 mil SOJ

- 400 mil SOJ

- 8 × 20mm TSOP 1

- 8 x 13.4mm sTSOP 1

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

• Low power consumption: STANDBY

- 18 mW / max CMOS

• 6T 0.18u CMOS technology

Pin arrangement

32-pin SOJ (300 mil)

32-pin SOJ (400 mil)

Logic block diagram

A15

CE2

A13

A11

A16

A14

A12

I/O0

I/O1

I/O2

GND

A10

Input buffer

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

I/O7

I/O0

512 x 256 x 8

Array

32-pin (8 x 20mm) TSOP I

32-pin (8 x 13.4mm) sTSOP1

(1,048,576)

A11

A10

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

A13

CE2

A15

Column decoder

Control

circuit

CE1

CE2

A16

A14

A12

Selection guide

-12

-15

-20

Unit

-10

Maximum address access time

Maximum output enable access time

Maximum operating current

Maximum CMOS standby current

3/24/04, v.1.2

Alliance Semiconductor

P. 1 of 9

12 3 4 5 6 7...9

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