Datasheet > AS7C31024-15HI

AS7C31024-15HI

更新时间： 2022-12-01 20:41:35

品牌	Logo	应用领域
ALSC		静态存储器光电二极管
页数	文件大小	规格书
9页	209K
描述
Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32

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AS7C31024-15HI 数据手册

October 2000

AS7C1024

AS7C31024

5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)

Features

• AS7C1024 (5V version)

• 2.0V data retention

• Easy memory expansion with CE1, CE2, OE inputs

• TTL/LVTTL-compatible, three-state I/O

• 32-pin JEDEC standard packages

- 300 mil SOJ

- 400 mil SOJ

- 8 × 20mm TSOP I

- 8 × 13.4 mm sTSOP I

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

• AS7C31024 (3.3V version)

• Industrial and commercial temperatures

• Organization: 131,072 words × 8 bits

• High speed

- 10/12/15/20 ns address access time

- 5/6/8/10 ns output enable access time

• Low power consumption: ACTIVE

- 825 mW (AS7C1024) / max @ 12 ns

- 360 mW (AS7C31024) / max @ 12 ns

• Low power consumption: STANDBY

- 55 mW (AS7C1024) / max CMOS

- 36 mW (AS7C31024) / max CMOS

Logic block diagram

Pin arrangement

32-pin SOJ (300 mil)

32-pin SOJ (400 mil)

32-pin TSOP I and sTSOP I

(8 x 20mm and 8 x 13.4mm)

V_CC

GND

A11

A15

CE2

A16

A14

A12

I/O0

I/O1

I/O2

GND

A10

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

Input buffer

A13

CE2

A15

A13

I/O7

I/O0

A16

A14

A12

A11

512×256×8

A10

Array

(1,048,576)

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

Column decoder

Control

circuit

CE1

CE2

Selection guide

AS7C1024-10 AS7C1024-12 AS7C1024-15 AS7C1024-20

AS7C31024-10 AS7C31024-12 AS7C31024-15 AS7C31024-20 Unit

Maximum address access time

Maximum output enable access time

AS7C1024

AS7C31024

AS7C1024

AS7C31024

150

100

140

125

110

Maximum operating current

Maximum CMOS standby current

Shaded areas contain advance information.

10/18/00

ALLIANCE SEMICONDUCTOR

12 3 4 5 6 7...9

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