High Performance
32K×9
AS7C259
AS7C259L
CMOS SRAM
32K×9 CMOS SRAM (Common I/O)
FEATURES
•
•
Organization: 32,768 words × 9 bits
• 2.0V data retention (L version)
• Equal access and cycle times
High speed
– 12/15/20/25/35 ns address access time
– 3/4/5/6/8 ns output enable access time
• Easy memory expansion with CE1, CE2, and OE inputs
• TTL-compatible, three-state I/O
•
Low power consumption
• 32-pin JEDEC standard packages
– 300 mil PDIP and SOJ
– Active:
– Standby: 11 mW max, CMOS I/O
2.75 mW max, CMOS I/O, L version
– Very low DC component in active power
633 mW max (10 ns cycle)
• ESD protection > 2000 volts
• Latch-up current > 200 mA
LOGIC BLOCK DIAGRAM
PIN ARRANGEMENT
DIP, SOJ
Vcc
GND
NC
NC
A8
A7
A6
A5
A4
A3
A2
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A14
CE2
WE
A13
A9
A10
A11
OE
A12
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
INPUT BUFFER
A0
A1
A2
A3
A4
A5
I/O8
I/O0
128 × 64 × 9
ARRAY
9
A1
A0
10
11
12
13
14
15
16
(294,912)
I/O0
I/O1
I/O2
I/O3
GND
A6
A14
WE
OE
COLUMN DECODER
CONTROL
CIRCUIT
CE1
CE2
A
7
A
8
A
9
A A A A
10 11 12 13
AS7C259-01
AS7C259-02
SELECTION GUIDE
7C259-12
7C259-15
7C259-20
7C259-25
7C259-35
Unit
Maximum Address Access Time
Maximum Output Enable Access Time
Maximum Operating Current
12
4
15
4
20
5
25
6
35
8
ns
ns
115
2.0
0.5
110
2.0
0.5
100
2.0
0.5
90
2.0
0.5
80
2.0
0.5
mA
mA
mA
Maximum CMOS Standby Current
L
Shaded areas contain advance information.
ALLIANCE SEMICONDUCTOR