Datasheet > AS7C256L-25JC

AS7C256L-25JC

更新时间： 2024-11-23 23:00:31

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
8页	128K
描述
High Performance 32Kx8 CMOS SRAM

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中文翻译

获取价格

数据手册

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AS7C256L-25JC 数据手册

High Performance

32K×8

AS7C256

AS7C256L

CMOS SRAM

32K×8 CMOS SRAM (Common I/O)

FEATURES

•

Organization: 32,768 words × 8 bits

• Equal access and cycle times

• Easy memory expansion with CE and OE inputs

• TTL-compatible, three-state I/O

High speed

– 10/12/15/20/25/35 ns address access time

– 3/3/4/5/6/8 ns output enable access time

• 28-pin JEDEC standard packages

•

Low power consumption

– 300 mil PDIP and SOJ

Socket compatible with 7C512 and 7C1024

– Active:

660 mW max (10 ns cycle)

– 330 mil SOIC

– Standby:

11 mW max, CMOS I/O

2.75 mW max, CMOS I/O, L version

– 8×13.4 TSOP

– Very low DC component in active power

2.0V data retention (L version)

• ESD protection > 2000 volts

• Latch-up current > 200 mA

•

LOGIC BLOCK DIAGRAM

PIN ARRANGEMENT

DIP, SOJ, SOIC

A14

A12

Vcc

A13

A11

Vcc

GND

INPUT BUFFER

A10

I/O7

I/O0

I/O7

I/O6

I/O5

I/O4

I/O3

I/O0

I/O1

I/O2

GND

256×128×8

ARRAY

(262,144)

A14

A11

A10

TSOP 8×13.4

I/O7

I/O6

I/O5

I/O4

I/O3

COLUMN DECODER

CONTROL

CIRCUIT

A13

Vcc

A A A A

10 11 12 13

AS7C256

A14

A12

GND

I/O2

I/O1

I/O0

AS7C256-01

AS7C256-02

SELECTION GUIDE

7C256-10 7C256-12 7C256-15 7C256-20 7C256-25 7C256-35 Unit

Maximum Address Access Time

Maximum Output Enable Access Time

Maximum Operating Current

120

2.0

0.5

115

2.0

0.5

110

2.0

0.5

100

2.0

0.5

2.0

0.5

2.0

0.5

Maximum CMOS Standby Current

ALLIANCE SEMICONDUCTOR

12 3 4 5 6 7 8

中文翻译

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AS7C256L-25PC	ALSC	获取价格	High Performance 32Kx8 CMOS SRAM
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