September 2001
AS7C256
AS7C3256
®
5V/ 3.3V 32K X 8 CMOS SRAM (Common I/ O)
Features
• AS7C256 (5V version)
• Very low power consumption: STANDBY
- 22 mW (AS7C256) / max CMOS I/ O
- 7.2 mW (AS7C3256) / max CMOS I/ O
• Easy memory expansion with CE and OE inputs
• TTL-compatible, three-state I/ O
• 28-pin JEDEC standard packages
- 300 mil PDIP
- 300 mil SOJ
- 8 × 13.4 mm TSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• AS7C3256 (3.3V version)
• Industrial and commercial temperature
• Organization: 32,768 words × 8 bits
• High speed
- 12/ 15/ 20 ns address access time
- 6, 7, 8 ns output enable access time
• Very low power consumption: ACTIVE
- 660mW (AS7C256) / max @ 12 ns
- 216mW (AS7C3256) / max @ 12 ns
Logic block diagram
Pin arrangement
28-pin TSOP 1 (8×13.4 mm)
V
28-pin DIP, SOJ (300 mil)
CC
GND
Input buffer
A14
A12
A7
A6
ꢀꢈ
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
V
CC
WE
A13
ꢀꢁ
OE
A11
A9
1
A10
CE
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(1)
(21) 28
(20) 27
(19) 26
(18) 25
(17) 24
(16) 23
(15) 22
(14) 21
(13) 20
(12) 19
(11) 18
(10) 17
(9) 16
(8) 15
2
3
I/ O7
I/ O6
I/ O5
I/ O4
I/ O3
GND
I/ O2
I/ O1
I/ O0
A0
A0
A1
A8
4
I/ O7
I/ O0
A13
WE
5
ꢀꢂ
6
A2
A3
256 X 128 X 8
Array
A4
A3
A2
A1
A11
OE
A10
CE
I/ O7
ꢃꢄꢅꢆ
I/ O5
I/ O4
ꢃꢄꢅꢇ
V
7
CC
AS7C256
AS7C3256
8
A14
A12
A7
9
(2)
A4
10
11
12
13
14
(3)
9
(4)
(262,144)
A6
A5
(5)
A5
A0
10
11
12
13
14
A6
(6)
A4
A1
A2
I/ O0
ꢃꢄꢅꢉ
ꢃꢄꢅꢊ
GND
(7)
A3
A14
17
16
15
Note: This part is compatible with both pin numbering
conventions used by various manufacturers.
WE
OE
CE
Column decoder
Control
circuit
A
7
A
8
A
9
A A A A
10 11 12 13
Selection guide
-12
12
6
-15
15
7
-20
20
8
Unit
ns
Maximum address access time
Maximum output enable access time
ns
AS7C256
120
60
4
115
55
4
110
50
4
mA
mA
mA
mA
Maximum operating current
AS7C3256
AS7C256
AS7C3256
Maximum CMOS standby current
2
2
2
9/ 18/ 01; v.1.6
Alliance Semiconductor
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