Datasheet > AS7C25512PFS36A-250BC

AS7C25512PFS36A-250BC

更新时间： 2024-11-28 03:09:47

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
21页	458K
描述
Standard SRAM, 512KX36, 6.5ns, CMOS, PBGA165, BGA-165

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December 2002

Advance Information

AS7C25512PFS32A

AS7C25512PFS36A

2.5V 512K × 32/ 36 pipelined burst synchronous SRAM

Features

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

• Boundary scan using IEEE 1149.1 JTAG function

• NTD™¹pipelined architecture available

(AS7C251MNTD18A, AS7C25512NTD32A/

AS7C25512NTD36A)

• Organization: 524,288 words × 32 or 36 bits

• Fast clock speeds to 250MHz in LVTTL/ LVCMOS

• Fast clock to data access: 2.6/ 2.8/ 3/ 3.4 ns

• Fast OEaccess time: 2.6/ 2.8/ 3/ 3.4 ns

• Fully synchronous register-to-register operation

• Single register flow-through mode

• Single-cycle deselect

• Asynchronous output enable control

• Available in 100-pin TQFP package and 165-ball BGA

• Individual byte write and global write

• Multiple chip enables for easy expansion

• 2.5V core power supply

1 NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks

mentioned in this document are the property of their respective owners.

Logic block diagram

LBO

CLK

ADV

CLK

CLR

Burst logic

ADSC

ADSP

512K × 32/ 36

Memory

array

CLK

A[18:0]

Address

36/ 32

GWE

BWE

DQ_d

Byte write

registers

CLK

DQ_c

Byte write

registers

CLK

DQ_b

Byte write

registers

CLK

DQ_a

Byte write

registers

CLK

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

Enable

CLK

Enable

delay

Power

down

CLK

36/ 32

DQ[a:d]

Selection guide

-250

-225

4.4

-200

-166

Units

Minimum cycle time

Maximum clock frequency

250

2.6

450

160

225

2.8

200

3.0

400

130

166

3.4

350

120

MHz

Maximum pipelined clock access time

Maximum operating current

425

150

Maximum standby current

Maximum CMOS standby current (DC)

12/ 2/ 02, v. 0.9.1

Alliance Semiconductor

1 of 21

12 3 4 5 6 7...21

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