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AS7C25512PFD32A-133TQC PDF预览

AS7C25512PFD32A-133TQC

更新时间: 2024-11-23 23:00:31
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
19页 523K
描述
2.5V 512K x 32/36 pipelined burst synchronous SRAM

AS7C25512PFD32A-133TQC 数据手册

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February 2005  
AS7C25512PFD32A  
AS7C25512PFD36A  
®
2.5V 512K × 32/36 pipelined burst synchronous SRAM  
Features  
• Organization: 524,288 words × 32 or 36 bits  
• Fast clock speeds to 166 MHz  
• Fast clock to data access: 3.5/3.8 ns  
• Fast OE access time: 3.5/3.8 ns  
• Fully synchronous register-to-register operation  
• Double-cycle deselect  
• Individual byte write and global write  
• Multiple chip enables for easy expansion  
• 2.5V core power supply  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
• Common data inputs and data outputs  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
Logic block diagram  
LBO  
CLK  
ADV  
ADSC  
ADSP  
CLK  
CE  
Burst logic  
CLR  
512K × 32/36  
Memory  
array  
19  
17  
19  
19  
D
CE  
CLK  
Q
A[18:0]  
Address  
register  
36/32  
36/32  
GWE  
BWE  
BWd  
D
Q
DQd  
Byte write  
registers  
CLK  
D
Q
DQc  
Byte write  
registers  
BWc  
BWb  
CLK  
D
Q
DQb  
Byte write  
registers  
CLK  
D
Q
DQa  
Byte write  
registers  
4
BWa  
CLK  
CE0  
CE1  
OE  
Output  
registers  
CLK  
D
Q
Q
CE2  
Input  
registers  
CLK  
Enable  
register  
CE  
CLK  
D
Enable  
delay  
register  
CLK  
Power  
down  
ZZ  
36/32  
DQ[a:d]  
OE  
Selection guide  
-166  
6
-133  
7.5  
133  
3.8  
270  
75  
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
166  
3.5  
290  
85  
MHz  
ns  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
40  
40  
2/10/05, v. 1.2  
Alliance Semiconductor  
1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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