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AS7C25512NTD36A-166TQCN PDF预览

AS7C25512NTD36A-166TQCN

更新时间: 2024-11-26 23:00:31
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
18页 428K
描述
2.5V 512K x 32/36 Pipelined SRAM with NTD

AS7C25512NTD36A-166TQCN 数据手册

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December 2004  
AS7C25512NTD32A  
AS7C25512NTD36A  
®
2.5V 512K × 32/36 Pipelined SRAM with NTDTM  
• Individual byte write and global write  
Features  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 2.5V core power supply  
• Self-timed write cycles  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
• Organization: 524,288 words × 32 or 36 bits  
• NTD architecture for efficient bus operation  
• Fast clock speeds to 166 MHz  
• Fast clock to data access: 3.5/3.8 ns  
• Fast OE access time: 3.5/3.8 ns  
• Fully synchronous operation  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
Logic block diagram  
19  
19  
Q
A[18:0]  
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
19  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
ADV / LD  
512K x 32/36  
SRAM  
LBO  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
CLK  
Output  
Register  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection guide  
-166  
6
-133  
7.5  
133  
3.8  
270  
75  
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
166  
3.5  
290  
85  
MHz  
ns  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
40  
40  
12/23/04, v 2.2  
Alliance Semiconductor  
P. 1 of 18  
Copyright © Alliance Semiconductor. All rights reserved.  

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