Datasheet > 存储 > SRAM> AS7C25512FT36A-10TQCN

AS7C25512FT36A-10TQCN

更新时间： 2024-11-23 22:13:35

品牌	Logo	应用领域
ALSC		内存集成电路静态存储器时钟
页数	文件大小	规格书
19页	525K
描述
2.5V 512K x 32/36 flowthrough burst synchronous SRAM

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数据手册

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AS7C25512FT36A-10TQCN 数据手册

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December 2004

AS7C25512FT32A

AS7C25512FT36A

2.5V 512K × 32/36 flowthrough burst synchronous SRAM

Features

• 2.5V core power supply

• Organization: 524,288 words × 32 or 36 bits

• Fast clock to data access: 7.5/8.5/10.0 ns

• Fast OE access time: 3.5/4.0 ns

• Fully synchronous flow-through operation

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Individual byte write and global write

• Multiple chip enables for easy expansion

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

CLK

Burst logic

CLR

512K × 32/36

Memory

array

CLK

A[18:0]

Address

36/32

GWE

BWE

BW_d

DQ_d

Byte write

registers

CLK

DQ_c

Byte write

registers

BW_c

BW_b

BW_a

CLK

DQ_b

Byte write

registers

CLK

DQ_a

Byte write

registers

CLK

CE0

CE1

Output

buffer

CE2

Input

registers

CLK

Enable

CLK

Enable

delay

CLK

Power

down

36/32

DQ[a:d]

Selection guide

-75

8.5

7.5

275

-85

-10

Units

Minimum cycle time

Maximum clock access time

Maximum operating current

Maximum standby current

8.5

250

230

Maximum CMOS standby current (DC)

12/23/04, v. 1.2

Alliance Semiconductor

1 of 19

12 3 4 5 6 7...19

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