Datasheet > 存储 > SRAM> AS7C252MPFS18A-133TQC

AS7C252MPFS18A-133TQC

更新时间： 2024-11-26 23:00:31

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
18页	508K
描述
2.5V 2M x 18 pipelined burst synchronous SRAM

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February 2005

AS7C252MPFS18A

2.5V 2M × 18 pipelined burst synchronous SRAM

Features

• Individual byte write and global write

• Multiple chip enables for easy expansion

• 2.5V core power supply

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

• Organization: 2,097,152 words × 18 bits

• Fast clock speeds to 200 MHz

• Fast clock to data access: 3.1/3.5/3.8 ns

• Fast OE access time: 3.1/3.5/3.8 ns

• Fully synchronous register-to-register operation

• Single-cycle deselect

• Asynchronous output enable control

• Available in 100-pin TQFP package

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

CLK

CLR

Burst logic

2M x 18

Memory

array

21 19

A[20:0]

Address

CLK

GWE

BW_b

DQb

Byte Write

registers

BWE

BW_a

CLK

DQa

Byte Write

registers

CLK

CE0

CE1

Output

registers

Input

registers

Enable

CLK

CE2

CLK

Enable

delay

CLK

Power

down

DQ[a,b]

Selection guide

-200

-166

-133

7.5

Units

Minimum cycle time

Maximum clock frequency

200

3.1

450

170

166

3.5

400

150

133

3.8

MHz

Maximum pipelined clock access time

Maximum operating current

Maximum standby current

350

140

Maximum CMOS standby current (DC)

2/14/05, v.1.3

Alliance Semiconductor

1 of 18

12 3 4 5 6 7...18

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