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AS7C252MPFD18A-133TQI PDF预览

AS7C252MPFD18A-133TQI

更新时间: 2024-11-23 22:26:39
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
18页 508K
描述
2.5V 2M x 18 pipelined burst synchronous SRAM

AS7C252MPFD18A-133TQI 数据手册

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February 2005  
AS7C252MPFD18A  
®
2.5V 2M × 18 pipelined burst synchronous SRAM  
Features  
• Individual byte write and global write  
• Multiple chip enables for easy expansion  
• 2.5V core power supply  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
• Common data inputs and data outputs  
• Organization: 2,097,152 words × 18 bits  
• Fast clock speeds to 200 MHz  
• Fast clock to data access: 3.1/3.5/3.8 ns  
• Fast OE access time: 3.1/3.5/3.8 ns  
• Fully synchronous register-to-register operation  
• Double-cycle deselect  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
Logic block diagram  
LBO  
CLK  
ADV  
ADSC  
ADSP  
CLK  
CS  
CLR  
Burst logic  
2M x 18  
Memory  
array  
21 19  
21  
21  
Q
D
A[20:0]  
Address  
CS  
register  
CLK  
18  
18  
2
GWE  
BWb  
D
DQb  
Q
Byte Write  
registers  
BWE  
BWa  
CLK  
D
Q
DQa  
Byte Write  
registers  
CLK  
CE0  
CE1  
OE  
Output  
registers  
D
Q
Q
Input  
registers  
Enable  
register  
CE  
CLK  
CE2  
CLK  
CLK  
D
Enable  
delay  
register  
CLK  
Power  
down  
ZZ  
OE  
18  
DQ[a,b]  
Selection guide  
-200  
-166  
-133  
7.5  
Units  
ns  
Minimum cycle time  
5
6
Maximum clock frequency  
200  
3.1  
450  
170  
90  
166  
3.5  
400  
150  
90  
133  
3.8  
MHz  
ns  
Maximum pipelined clock access time  
Maximum operating current  
Maximum standby current  
350  
140  
90  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
2/11/05, v.1.1  
Alliance Semiconductor  
1 of 18  
Copyright © Alliance Semiconductor. All rights reserved.  

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