Datasheet > AS7C252MNTD18A

AS7C252MNTD18A

更新时间： 2024-11-23 22:29:59

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
18页	436K
描述
2.5V 2M x 18 Pipelined SRAM with NTD

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数据手册

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AS7C252MNTD18A 数据手册

January 2005

AS7C252MNTD18A

2.5V 2M × 18 Pipelined SRAM with NTD^TM

Features

• Available in 100-pin TQFP packages

• Byte write enables

• Clock enable for operation hold

• Multiple chip enables for easy expansion

• 2.5V core power supply

• Organization: 2,097,152 words × 18 bits

• NTD^™architecture for efficient bus operation

• Fast clock speeds to 200 MHz

• Fast clock to data access: 3.2/3.5/3.8 ns

• Fast OE access time: 3.2/3.5/3.8 ns

• Fully synchronous operation

• Self-timed write cycles

• Interleaved or linear burst modes

• Snooze mode for standby operation

• Pipelined mode

• Common data inputs and data outputs

• Asynchronous output enable control

Logic block diagram

A[20:0]

Address

Burst logic

CLK

CE0

CE1

CE2

Write delay

addr. registers

CLK

R/W

BWa

Control

logic

CLK

BWb

ADV / LD

LBO

2 M x 18

SRAM

Array

CLK

DQ[a,b]

Data

Input

CLK

CEN

CLK

Output

DQ[a,b]

Selection guide

-200

-166

-133

7.5

Units

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

200

3.2

450

170

166

3.5

400

150

133

3.8

MHz

350

140

Maximum CMOS standby current (DC)

1/17/05, V 1.2

Alliance Semiconductor

P. 1 of 18

12 3 4 5 6 7...18

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