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AS7C252MFT18A-10TQC PDF预览

AS7C252MFT18A-10TQC

更新时间: 2024-11-23 22:30:11
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
19页 509K
描述
2.5V 2M x 18 Flow-through synchronous SRAM

AS7C252MFT18A-10TQC 数据手册

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January 2005  
AS7C252MFT18A  
®
2.5V 2M × 18 Flow-through synchronous SRAM  
Features  
• Organization: 2,097152 words × 18 bits  
• Fast clock to data access: 7.5/8.5/10 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous flow-through operation  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
• Individual byte write and global write  
• Multiple chip enables for easy expansion  
• 2.5V core power supply  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
• Common data inputs and data outputs  
Logic block diagram  
LBO  
CLK  
ADV  
ADSC  
ADSP  
CLK  
CS  
Burst logic  
2M x 18  
CLR  
Memory  
array  
21 19  
21  
21  
Q
D
A[20:0]  
Address  
CS  
register  
CLK  
18  
18  
2
GWE  
BWb  
D
DQb  
Q
Byte Write  
registers  
BWE  
BWa  
CLK  
D
Q
DQa  
Byte Write  
registers  
CLK  
CE0  
CE1  
OE  
Output  
D
Q
Q
Input  
registers  
Enable  
register  
CE  
CLK  
CE2  
registers  
CLK  
CLK  
D
Enable  
delay  
register  
CLK  
Power  
down  
ZZ  
OE  
18  
DQ[a,b]  
Selection guide  
-75  
8.5  
7.5  
325  
130  
90  
-85  
10  
-10  
12  
Units  
ns  
Minimum cycle time  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
Maximum CMOS standby current (DC)  
8.5  
300  
130  
90  
10  
ns  
275  
130  
90  
mA  
mA  
mA  
1/17/05, v 1.2  
Alliance Semiconductor  
1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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