Datasheet > AS7C251MPFD18A-133BIN

AS7C251MPFD18A-133BIN

更新时间： 2024-11-29 19:43:23

品牌	Logo	应用领域
ALSC		时钟 ISM频段静态存储器内存集成电路
页数	文件大小	规格书
23页	584K
描述
Standard SRAM, 1MX18, 3.8ns, CMOS, PBGA165, LEAD FREE, BGA-165

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中文翻译

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数据手册

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March 2004

AS7C251MPFD18A

2.5V 1M x 18 pipelined burst synchronous SRAM

Features

• Multiple chip enables for easy expansion

• 2.5V core power supply

NTD™¹pipelined architecture available

(AS7C251MNTD18A, AS7C25512NTD32A/

AS7C25512NTD36A)

• Organization: 1,048,576 x18 bits

• Fast clock speeds to 166 MHz in LVTTL/LVCMOS

• Fast clock to data access: 3.5/3.8 ns

• Fast OE access time: 3.5/3.8 ns

•

• Fully synchronous register-to-register operation

• Boundary scan using IEEE 1149.1 JTAG function

•

Dual-cycle deselect

Single-cycle deselect also available

(AS7C251MPFS18A

•

)

• Asynchronous output enable control

• Available 100-pin TQFP and 165-ball BGA packages

• Byte write enables

1 NTD™ is a trademark of Alliance Semiconductor Corporation. All

trademarks mentioned in this document are the property of their respective

owners.

Logic block diagram

LBO

CLK

ADV

CLK

CLR

ADSC

ADSP

Burst logic

20 18

1M x 18

Memory

array

A[19:0]

Address

^CSregister

CLK

GWE

BW_b

Byt^De^QW^brite

registers

BWE

BW_a

CLK

Byt^De^QW^arite

registers

CLK

CE0

CE1

CE2

^DEnable

Input

Output

registers

CLK

^DEnable

Power

delay

down

CLK

DQ[a,b]

Selection guide

-166

-133

7.5

133

3.8

270

Units

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

166

3.5

290

MHz

3/25/04, v. 1.0

Alliance Semiconductor

1 of 23

12 3 4 5 6 7...23

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AS7C251MPFD18A-133TQI	ALSC	获取价格	2.5V 1M x 18 pipelined burst synchronous SRAM
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AS7C251MPFD18A-166TQCN	ALSC	获取价格	2.5V 1M x 18 pipelined burst synchronous SRAM
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