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AS7C251MNTD18A-133BIN PDF预览

AS7C251MNTD18A-133BIN

更新时间: 2024-09-21 20:04:43
品牌 Logo 应用领域
ALSC 时钟ISM频段静态存储器内存集成电路
页数 文件大小 规格书
22页 445K
描述
ZBT SRAM, 1MX18, 10ns, CMOS, PBGA165, LEAD FREE, BGA-165

AS7C251MNTD18A-133BIN 数据手册

 浏览型号AS7C251MNTD18A-133BIN的Datasheet PDF文件第2页浏览型号AS7C251MNTD18A-133BIN的Datasheet PDF文件第3页浏览型号AS7C251MNTD18A-133BIN的Datasheet PDF文件第4页浏览型号AS7C251MNTD18A-133BIN的Datasheet PDF文件第5页浏览型号AS7C251MNTD18A-133BIN的Datasheet PDF文件第6页浏览型号AS7C251MNTD18A-133BIN的Datasheet PDF文件第7页 
April 2004  
AS7C251MNTD18A  
®
2.5V 1M x 18 SRAM with NTDTM  
Features  
• Organization: 1,048,576 words × 18 bits  
• NTD™1 architecture for efficient bus operation  
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.5/3.8 ns  
• Fast OE access time: 3.5/3.8 ns  
• Asynchronous output enable control  
• Available in 100-pin TQFP and 165-ball BGA pack-  
age  
• Byte write enables  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 2.5V core power supply  
• Fully synchronous operation  
• Flow-through or pipelined mode  
• Self-timed write cycles  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
1. NTDTM is a trademark of Alliance Semiconductor Corporation. All trade-  
marks mentioned in this document are the property of their respective owners.  
Boundary scan using IEEE 1149.1 JTAG function  
Logic block diagram  
20  
20  
Q
A[19:0]  
D
Address  
register  
burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
20  
CLK  
R/W  
BWa  
BWb  
Control  
logic  
CLK  
ADV / LD  
FT  
1M x 18  
SRAM  
array  
LBO  
ZZ  
CLK  
18  
18  
DQ [a,b]  
Data  
input  
register  
D
Q
18  
18  
CLK  
18  
CLK  
CEN  
CLK  
Output  
register  
OE  
18  
OE  
DQ [a,b]  
Selection guide  
-166  
6
-133  
7.5  
133  
3.8  
270  
75  
Units  
ns  
Minimum cycle time  
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
166  
3.5  
290  
85  
MHz  
ns  
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
40  
40  
4/30/04, v.2.1  
Alliance Semiconductor  
P. 1 of 22  
Copyright © Alliance Semiconductor. All rights reserved.  

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