Datasheet > AS7C251MFT36A-85BCN

AS7C251MFT36A-85BCN

更新时间： 2024-11-25 20:58:39

品牌	Logo	应用领域
ALSC		时钟 ISM频段静态存储器内存集成电路
页数	文件大小	规格书
23页	578K
描述
Standard SRAM, 1MX36, 8.5ns, CMOS, PBGA165, LEAD FREE, BGA-165

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April 2004

AS7C251MFT32A

AS7C251MFT36A

2.5V 1M × 32/36 Flow-through synchronous SRAM

Features

• Organization: 1,048,576 words × 32 or 36 bits

• Fast clock to data access: 6.5/7.5/8.5 ns

• Fast OE access time: 3.5/3.5/4.0 ns

• Common data inputs and data outputs

• Boundary scan using IEEE 1149.1 JTAG function

• NTD™ pipelined architecture available

• Fully synchronous flow-through operation

• Asynchronous output enable control

• Available in 100-pin TQFP package and 165-ball BGA

• Individual byte write and global write

• Multiple chip enables for easy expansion

• 2.5V core power supply

(AS7C252MNTD18A, AS7C251MNTD32A/

AS7C251MNTD36A)

1 NTD™ is a trademark of Alliance Semiconductor Corporation. All

trademarks mentioned in this document are the property of their

respective owners.

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

CLK

Burst logic

CLR

1M × 32/36

Memory

array

CLK

A[19:0]

Address

32/36

GWE

BWE

BW_d

DQ_d

Byte write

registers

CLK

DQ_c

Byte write

registers

BW_c

BW_b

CLK

DQ_b

Byte write

registers

CLK

DQ_a

Byte write

registers

BW_a

CLK

CE0

CE1

Output

registers

CE2

Input

registers

CLK

Enable

CLK

Enable

Power

down

delay

CLK

32/36

DQ[a:d]

Selection guide

-65

7.5

-75

-85

Units

Minimum cycle time

8.5

7.5

Maximum clock access time

Maximum operating current

Maximum standby current

6.5

8.5

270

130

110

310

140

110

290

130

110

Maximum CMOS standby current (DC)

4/26/04, v 1.0

Alliance Semiconductor

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12 3 4 5 6 7...23

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AS7C251MFT36A-85BIN	ALSC	获取价格	Standard SRAM, 1MX36, 8.5ns, CMOS, PBGA165, LEAD FREE, BGA-165
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