Datasheet > 存储 > SRAM> AS7C251MFT32A-85TQCN

AS7C251MFT32A-85TQCN

更新时间： 2024-11-24 22:53:55

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
19页	521K
描述
2.5V 1M x 32/36 Flow-through synchronous SRAM

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AS7C251MFT32A-85TQCN 数据手册

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January 2005

AS7C251MFT32A

AS7C251MFT36A

2.5V 1M × 32/36 Flow-through synchronous SRAM

Features

• Organization: 1,048,576 words × 32 or 36 bits

• Fast clock to data access: 7.5/8.5/10 ns

• Fast OE access time: 3.5/4.0 ns

• Fully synchronous flow-through operation

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Individual byte write and global write

• Multiple chip enables for easy expansion

• 2.5V core power supply

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

CLK

Burst logic

CLR

1M × 32/36

Memory

array

CLK

A[19:0]

Address

32/36

GWE

BWE

BW_d

DQ_d

Byte write

registers

CLK

DQ_c

Byte write

registers

BW_c

BW_b

CLK

DQ_b

Byte write

registers

CLK

DQ_a

Byte write

registers

BW_a

CLK

CE0

CE1

Output

registers

CE2

Input

registers

CLK

Enable

CLK

Enable

Power

down

delay

CLK

32/36

DQ[a:d]

Selection guide

-75

8.5

7.5

325

130

-85

-10

Units

Minimum cycle time

8.5

300

130

Maximum clock access time

Maximum operating current

Maximum standby current

275

130

Maximum CMOS standby current (DC)

1/17/05, v 1.2

Alliance Semiconductor

1 of 19

12 3 4 5 6 7...19

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