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AS7C251MFT18A-10TQCN PDF预览

AS7C251MFT18A-10TQCN

更新时间: 2024-11-24 22:30:11
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
19页 512K
描述
2.5V 1M x 18 flowthrough burst synchronous SRAM

AS7C251MFT18A-10TQCN 数据手册

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December 2004  
AS7C251MFT18A  
®
2.5V 1M x 18 flowthrough burst synchronous SRAM  
Features  
Individual byte write and global write  
• Organization: 1,048,576 words x18 bits  
• Fast clock to data access: 7.5/8.5/10 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous flow-through operation  
• Asynchronous output enable control  
• Available 100-pin TQFP package  
• Multiple chip enables for easy expansion  
• 2.5V core power supply  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
Logic block diagram  
LBO  
Burst logic  
CLK  
ADV  
CLK  
CS  
CLR  
ADSC  
ADSP  
1M x 18  
Memory  
array  
20 18  
20  
20  
Q
D
A[19:0]  
Address  
register  
CS  
CLK  
18  
18  
2
GWE  
BWb  
D
Q
DQb  
Byte Write  
registers  
BWE  
BWa  
CLK  
D
Q
DQa  
Byte Write  
registers  
CLK  
CE0  
CE1  
OE  
Output  
buffers  
D
Q
Q
Input  
registers  
Enable  
register  
CE  
CLK  
CE2  
CLK  
D
Enable  
delay  
register  
CLK  
Power  
down  
ZZ  
OE  
18  
DQ[a,b]  
Selection guide  
-75  
8.5  
7.5  
275  
90  
-85  
-10  
Units  
ns  
Minimum cycle time  
10  
8.5  
250  
80  
12  
10  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
Maximum CMOS standby current (DC)  
ns  
230  
80  
mA  
mA  
mA  
60  
60  
60  
12/24/04, v. 1.2  
Alliance Semiconductor  
1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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