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AS7C181026LL-70BI PDF预览

AS7C181026LL-70BI

更新时间: 2024-11-25 19:10:51
品牌 Logo 应用领域
ALSC 静态存储器内存集成电路
页数 文件大小 规格书
10页 182K
描述
Standard SRAM, 64KX16, 70ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, CSP, BGA-48

AS7C181026LL-70BI 数据手册

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• Optimized design for battery operated portable systems  
• Intelliwatt™ active power reduction circuitry  
• Organization: 65,536 words × 16 bits  
• 1.65V to 1.95V operating range  
• High speed  
- 55*/ 70/ 100 ns address access time  
Low power consumption  
JEDEC registered packaging  
- 44-pin TSOP II package  
- 48-ball csp 8mm × 6mm BGA  
Center power and ground pins for low noise  
ESD protection 2000 volts  
Latch-up current 200 mA  
• Industrial temperature range available (-40 to +85 °C)  
• Other voltage versions available  
- 2.3V to 3.0V (AS7C251026LL)  
- Active: 19.5 mW max (100 ns cycle)  
- Standby: 2 µW max  
- Very low DC component in active power, 20 µA  
• 1.20V data retention  
- 2.7V to 3.6V (AS7C31026LL)  
Easy memory expansion with CE, OE inputs  
LVTTL/ LVCMOS-compatible, three-state I/ O  
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A0  
VDD  
A1  
A2  
64K × 16  
Array  
V
SS  
A3  
A4  
A5  
A6  
A7  
TSOP II  
Power  
reduction  
I/ O0–I/ O7  
I/ O8–I/ O15  
I/ O  
buffer  
48-CSP Ball-Grid-Array package  
Control circuit  
1
2
3
4
5
6
A
B
C
D
E
LB  
OE  
A
A
A
NC  
Column decoder  
0
1
2
WE  
I/ O8 UB  
I/ O9 I/ O10  
A
A
CE I/ O0  
I/ O1 I/ O2  
I/ O3 VDD  
3
4
A
A
6
5
UB  
OE  
LB  
V
I/ O11 NC  
A
7
SS  
VDD I/ O12 NC  
NC I/ O4  
V
SS  
F
I/ O14 I/ O13  
I/ O15 NC  
A
A
I/ O5 I/ O6  
WE I/ O7  
14  
15  
CE  
G
H
A
A
13  
12  
NC  
A
A
A
A
11  
NC  
8
9
10  
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7C181026LL-55*  
7C181026LL-70  
7C181026LL-100  
Unit  
ns  
Maximum address access time  
55  
25  
19  
1
70  
35  
15  
1
100  
50  
10  
1
Maximum output enable access time  
Maximum operating current  
ns  
mA  
µA  
Maximum standby current  
*For availability of 55 ns device, contact Alliance.  
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Copyright ©1998 Alliance Semiconductor. All rights reserved.  

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