January 2001
Advance Information
AS7C1026A
AS7C31026A
®
5V/3.3V 64K X 16 CMOS SRAM
Features
• Latest 6T 0.25u CMOS technology
• 2.0V data retention
• AS7C1026A (5V version)
• AS7C31026A (3.3V version)
• Industrial and commercial versions
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
• Low power consumption: ACTIVE
- 660 mW (AS7C1026A) / max @ 10 ns
- 324 mW (AS7C31026A) / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1026A) / max CMOS I/O
- 36 mW (AS7C31026A) / max CMOS I/O
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin 400 mil TSOP II
- 48-ball 6 mm × 8 mm CSP mBGA
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement
Logic block diagram
48-CSP mini Ball-Grid-Array Package
44-Pin SOJ, TSOP II (400 mil)
A0
1
2
3
4
5
6
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
A4
A3
A2
A1
A0
V
A1
CC
A
B
C
D
E
LB
OE
A0
A3
A1
A2
NC
A2
64K × 16
Array
GND
I/O8 UB
A4 CE I/O0
A6 I/O1 I/O2
A7 I/O3 VDD
NC I/O4 VSS
A3
A4
I/O9 I/O10 A5
VSS I/O11 NC
VDD I/O12 NC
CE
A5
A6
A7
I/O0
I/O1
I/O2
I/O3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
CC
I/O0–I/O7
I/O
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
V
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
Control circuit
CC
buffer
I/O8–I/O15
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Column decoder
H
NC
A8
A9 A10 A11 NC
WE
UB
OE
LB
CE
Selection guide
AS7C1026A-10
AS7C1026A-12
AS7C1026A-15
AS7C1026A-20
AS7C31026A-10 AS7C31026A-12 AS7C31026A-15 AS7C31026A-20 Unit
Maximum address access time
10
3
12
3
15
4
20
5
ns
Maximum output enable access time
ns
AS7C1026A
120
90
10
10
110
80
10
10
100
80
10
10
100
80
15
15
mA
mA
mA
mA
Maximum operating current
AS7C31026A
AS7C1026A
AS7C31026A
Maximum CMOS standby
current
2/6/01; V.0.9
Alliance Semiconductor
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