March 2001
AS7C1026
AS7C31026
®
5V/3.3V 64K×16 CMOS SRAM
• Low power consumption: STANDBY
Features
• AS7C1026 (5V version)
• AS7C31026 (3.3V version)
- 28 mW (AS7C1026) / max CMOS I/O
- 18 mW (AS7C31026) / max CMOS I/O
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin 400 mil TSOP II
- 48-ball 6 mm × 8 mm CSP mBGA
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Industrial and commercial versions
• Organization: 65,536 words x 16 bits
• Center power and ground pins for low noise
• High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
- 880 mW (AS7C1026) / max @ 12 ns
- 396 mW (AS7C31026) / max @ 12 ns
Logic block diagram
Pin arrangement
44-Pin SOJ, TSOP II (400 mil)
A0
VCC
A1
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
A4
A3
A2
A1
A0
A2
64K × 16
GND
A3
48-CSP mini Ball-Grid-Array Package
Array
A4
1
2
3
4
5
6
A5
A6
A7
CE
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A
B
C
D
E
LB
OE
A0
A3
A1
A2
NC
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
I/O8 UB
A4 CE I/O0
A6 I/O1 I/O2
A7 I/O3 VDD
NC I/O4 VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O0–I/O7
I/O8–I/O15
I/O
buffer
I/O9 I/O10 A5
VSS I/O11 NC
VDD I/O12 NC
Control circuit
Column decoder
WE
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
UB
OE
LB
H
NC
A8
A9 A10 A11 NC
CE
Selection guide
AS7C1026-12
AS7C1026-15
AS7C1026-20
AS7C31026-12
AS7C31026-15
AS7C31026-20
Unit
ns
Maximum address access time
12
6
15
8
20
10
Maximum output enable access time
ns
AS7C1026
AS7C31026
AS7C1026
AS7C31026
160
110
10
150
100
10
140
90
mA
mA
mA
mA
Maximum operating current
15
Maximum CMOS standby current
10
10
15
Shaded areas indicate preliminary information.
3/23/01; v.1.0
Alliance Semiconductor
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