January 2001
Advance Information
AS7C1025A
AS7C31025A
®
5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout)
• Latest 6T 0.25u CMOS technology
• 2.0V data retention
Features
• AS7C1025A (5V version)
• AS7C31025A (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
• Low power consumption: ACTIVE
- 660 mW (AS7C1025A) / max @ 10 ns (5V)
- 324 mW (AS7C31025A) / max @ 10 ns (3.3V)
• Low power consumption: STANDBY
- 55 mW (AS7C1025A) / max CMOS (5V)
- 36 mW (AS7C31025A) / max CMOS (3.3V)
• Easy memory expansion with CE
• Center power and ground
, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin, TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement
32-pin TSOP II
A0
A1
A2
1
2
3
32
31
30
29
A16
A15
A14
A13
OE
I/O7
I/O6
GND
Logic block diagram
A3
4
28
27
26
25
24
23
22
21
CE
I/O0
I/O1
5
6
7
8
9
10
11
12
V
CC
V
CC
GND
I/O2
I/O3
WE
V
CC
GND
I/O5
I/O4
A12
A11
A10
A9
Input buffer
20
19
18
17
13
14
15
16
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O7
I/O0
A8
512
×256×8
Array
(1,048,576)
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A16
A0
1
32
31
30
A15
A14
A13
OE
I/O7
A1
A2
A3
CE
I/O0
I/O1
2
3
4
5
6
7
29
28
27
26
25
24
23
22
21
20
19
WE
Control
circuit
Column decoder
I/O6
GND
OE
CE
V
8
CC
V
GND
I/O2
I/O3
WE
A4
A5
A6
A7
9
10
11
12
13
14
15
16
CC
I/O5
I/O4
A12
A11
A10
A9
18
17
A8
Selection guide
AS7C1025A-10
AS7C31025A-10 AS7C31025A-12
AS7C1025A-12
AS7C1025A-15
AS7C31025A-15
AS7C1025A-20
AS7C31025A-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access
time
3
3
4
5
ns
Maximum
operating
current
AS7C1025A
AS7C31025A
AS7C1025A
AS7C31025A
120
90
110
80
100
80
100
80
mA
mA
mA
mA
Maximum
CMOS standby
current
10
10
10
15
10
10
10
15
2/6/01; V.0.9
Alliance Semiconductor
P. 1 of 8
Copyright © Alliance Semiconductor. All rights reserved.