Datasheet > 存储 > SRAM> AS7C1025-20TI

AS7C1025-20TI

更新时间： 2024-11-05 22:53:55

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
9页	189K
描述
5V/3.3V 128K x8 CMOS SRAM (Revolutionary pinout)

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中文翻译

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数据手册

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AS7C1025-20TI 数据手册

March 2001

AS7C1025

AS7C31025

5V/3.3V 128Kx8 CMOS SRAM (Revolutionary pinout)

Features

• AS7C1025 (5V version)

• Low power consumption: STANDBY

- 27.5 mW (AS7C1025) / max CMOS (5V)

• AS7C31025 (3.3V version)

• Industrial and commercial temperatures

• Organization: 131,072 words × 8 bits

• High speed

- 12/15/20 ns address access time

- 6,7,8 ns output enable access time

• Low power consumption: ACTIVE

- 715 mW (AS7C1025) / max @ 12 ns (5V)

- 360 mW (AS7C31025) / max @ 12 ns (3.3V)

- 1.8 mW (AS7C31025) / max CMOS (3.3V)

• 2.0V data retention

• Easy memory expansion with CE, OE inputs

• Center power and ground

• TTL/LVTTL-compatible, three-state I/O

• JEDEC-standard packages

- 32-pin, 300 mil SOJ

- 32-pin, 400 mil SOJ

- 32-pin TSOP II

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Logic block diagram

Pin arrangement

32-pin TSOP II

A16

A15

A14

A13

I/O7

I/O6

GND

Input buffer

I/O0

I/O1

I/O7

I/O0

GND

I/O2

I/O3

I/O5

I/O4

A12

A11

A10

512×256×8

Array

(1,048,576)

32-pin SOJ (300 mil)

32-pin SOJ (400 mil)

Control

circuit

Column decoder

A16

A15

A14

A13

I/O7

I/O6

GND

I/O0

I/O1

GND

I/O2

I/O3

I/O5

I/O4

A12

A11

A10

Selection guide

AS7C1025-12

AS7C31025-12

AS7C1025-15

AS7C31025-15

AS7C1025-20

AS7C31025-20

Unit

Maximum address access time

Maximum output enable access time

AS7C1025

AS7C31025

AS7C1025

AS7C31025

130

100

Maximum operating current

Maximum CMOS standby current

Shaded areas contain advance information.

3/23/01; v.1.0

Alliance Semiconductor

P. 1 of 9

12 3 4 5 6 7...9

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