Datasheet > AS6VA5128-HRI

AS6VA5128-HRI

更新时间： 2022-12-01 19:33:20

品牌	Logo	应用领域
ALSC		静态存储器光电二极管
页数	文件大小	规格书
11页	199K
描述
Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, REVERSE, TSOP2-32

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AS6VA5128-HRI 数据手册

June 2000

AS6VA5128

2.7V to 3.3V 512K × 8 Intelliwatt™ low-power CMOS SRAM with one chip enable

Features

• AS6VA5128

• Easy memory expansion with CS, OE inputs

• Smallest footprint packages

- 36(48)-ball FBGA

• Intelliwatt™ active power circuitry

• Industrial and commercial temperature ranges available

• Organization: 524,288 words × 8 bits

• 2.7V to 3.3V at 55 ns

• Low power consumption: ACTIVE

- 132 mW at 3.3V and 55 ns

• Low power consumption: STANDBY

- 66 µW max at 3.3V

- 32-pin TSOP I (available September 2000)

- 32-pin sTSOP I (available September 2000)

- 32-pin TSOP II (forward) (available September 2000)

- 32-pin TSOP II (reverse) (available September 2000)

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

• 1.2V data retention

• Equal access and cycle times

Pin arrangement

Logic block diagram

A18

A16

A14

A18

A16

A14

A12

GND

A15

A17

A13

A15

A17

A13

Input buffer

A12

A11

I/ O8

I/ O1

32-pin TSOPII

(Forward)

32-pin TSOPII

(Reverse)

A11

A10

I/ O8

I/ O7

I/ O6

I/ O5

A10

512K

× 8

Array

(4,194,304)

I/ O8

I/ O7

I/ O6

I/ O5

20 I/ O1

18 I/ O3

I/ O1

I/ O2

I/ O3

I/ O2

I/ O4

Column decoder

Control

circuit

A11

A10

I/ O8

I/ O7

I/ O6

I/ O5

I/ O4

A13

48-CSP BGA Package (shading indicates no ball)

A17

A15

32-pin TSOPII

32-pin sTSOPI

(Forward)

A18

A16

A14

A12

I/ O3

I/ O2

I/ O1

I/ O₅

I/ O₆

I/ O₁

I/ O₂

V_CC

I/ O₇

I/ O₈

V_SS

I/ O₃

I/ O₄

Selection guide

V_CCRange

Power Dissipation

Operating (I_CC1

)

Standby (I_SB2)

Min

(V)

Typ²

(V)

Max

(V)

Speed

(ns)

Product

Max (mA)

Max (µA)

AS6VA5128

2.7

3.0

3.3

7/ 14/ 00

ALLIANCE SEMICONDUCTOR

12 3 4 5 6 7...11

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