5秒后页面跳转
AS6UA5128-100HFI PDF预览

AS6UA5128-100HFI

更新时间: 2024-01-27 08:24:53
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
11页 218K
描述
SRAM

AS6UA5128-100HFI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
风险等级:5.92

AS6UA5128-100HFI 数据手册

 浏览型号AS6UA5128-100HFI的Datasheet PDF文件第2页浏览型号AS6UA5128-100HFI的Datasheet PDF文件第3页浏览型号AS6UA5128-100HFI的Datasheet PDF文件第4页浏览型号AS6UA5128-100HFI的Datasheet PDF文件第5页浏览型号AS6UA5128-100HFI的Datasheet PDF文件第6页浏览型号AS6UA5128-100HFI的Datasheet PDF文件第7页 
Advance information  
June 2000  
AS6UA5128  
1.65V to 3.6V 512K×8 Intelliwatt low-power CMOS SRAM with one chip enable  
Low power consumption: STANDBY  
- 72 µW max at 3.6V  
- 41 µW max at 2.7V  
- 28 µW max at 2.3V  
• 1.2V data retention  
Equal access and cycle times  
Easy memory expansion with CS, OE inputs  
Smallest footprint packages  
Features  
AS6UA5128  
• Intelliwatt™ active power circuitry  
• Industrial and commercial temperature ranges available  
• Organization: 524,288 words × 8 bits  
• 2.7V to 3.6V at 55 ns  
• 2.3V to 2.7V at 70 ns  
• 1.65V to 2.3V at 100 ns  
Low power consumption: ACTIVE  
- 144 mW at 3.6V and 55 ns  
- 68 mW at 2.7V and 70 ns  
- 36(48)-ball FBGA  
- 32-pin TSOP I (available September 2000)  
- 32-pin sTSOP I (available September 2000)  
- 32-pin TSOP II (forward) (available September 2000)  
- 32-pin TSOP II (reverse) (available September 2000)  
ESD protection 2000 volts  
Latch-up current 200 mA  
- 28 mW at 2.3 V and 100 ns  
Logic block diagram  
V
CC  
Pin arrangement  
GND  
Input buffer  
A18  
A16  
A14  
1
2
3
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
32  
31  
30  
29  
28  
27  
26  
25  
24  
V
A18  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
V
CC  
CC  
A15  
A17  
WE  
A13  
A8  
A15  
A17  
WE  
A13  
A8  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
I/ O8  
I/ O1  
A12  
4
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
512K  
×8  
Array  
(4,194,304)  
A9  
A11  
A9  
32-TSOPII  
(Forward)  
32-TSOPII  
(Reverse)  
A11  
OE  
A10  
CS  
I/ O8  
I/ O7  
I/ O6  
I/ O5  
OE  
A10  
A2  
A1  
A0  
23  
22  
21  
CS  
I/ O8  
I/ O7  
I/ O6  
I/ O5  
20 I/ O1  
19  
18 I/ O3  
17  
I/ O1  
I/ O2  
I/ O3  
I/ O2  
WE  
OE  
CS  
Column decoder  
Control  
circuit  
V
I/ O4  
V
SS  
I/ O4  
SS  
A11  
A9  
A8  
1
2
3
4
5
6
7
8
32  
OE  
A10  
CS  
I/ O8  
I/ O7  
I/ O6  
I/ O5  
I/ O4  
31  
30  
29  
A13  
WE  
A17  
A15  
36(48)-CSP BGA Package (shading indicates no ball)  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
3
4
5
6
32-TSOPI  
32-sTSOPI  
(Forward)  
V
CC  
A
B
C
D
E
F
G
H
A
I/ O5  
I/ O6  
A
NC  
WE  
NC  
A
A
A
9
10  
11  
A18  
A16  
A14  
A12  
0
1
3
6
8
V
SS  
I/ O3  
I/ O2  
I/ O1  
A0  
A1  
A2  
A
A
A
I/ O1  
I/ O2  
VCC  
VSS  
I/ O3  
I/ O4  
2
4
7
12  
A
5
13  
14  
15  
16  
A7  
A6  
A5  
A4  
V
SS  
VCC  
I/ O7  
I/ O8  
A3  
A
A
18  
CS  
17  
OE  
A
A
15  
16  
A
A
A
A
A
A
14  
9
10  
11  
12  
13  
Selection guide  
VCC Range  
Power Dissipation  
Typ2  
(V)  
3.0  
2.5  
2.0  
Max  
Speed  
(ns)  
55  
70  
100  
Operating (ICC1  
)
Standby (ISB2)  
Min  
(V)  
2.7  
2.3  
1.65  
Product  
AS6UA5128  
AS6UA5128  
AS6UA5128*  
(V)  
3.6  
2.7  
2.3  
Max (mA)  
Max (µA)  
2
1
1
20  
15  
12  
* Shaded areas indicate advance information.  
7/ 14/ 00  
ALLIANCE SEMICONDUCTOR  
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.