Preliminary information
June 2000
AS6UA25617
1.65V to 3.6V 256K×16 Intelliwatt™ low power CMOS SRAM with two chip enables
• Low power consumption: STANDBY
- 72 µW max at 3.6V
Features
• AS6UA25617
- 41 µW max at 2.7V
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 262,144 words × 16 bits
• 2.7V to 3.6V at 55 ns
• 2.3V to 2.7V at 70 ns
• 1.65V to 2.3V at 100 ns
- 28 µW max at 2.3V
• 1.2V data retention
• Equal access and cycle times
• Easy memory expansion with CS1, CS2, OE inputs
• Smallest footprint package
- 400-mil 44-pin TSOP II
- 48-ball FBGA
• CS1 and CS2 for chip selection
• Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
- 28 mW at 2.3 V and 100 ns
Pin arrangement (top view)
400-pin 400-mil TSOP II
Logic block diagram
A0
A1
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A0
2
A16
V
A1
A2
A2
3
A15
DD
A3
4
OE
1024 × 256 × 16
Array
(4,194,304)
A4
5
UB
V
A3
SS
CS1
I/ O1
6
LB
A4
I/ O16
I/ O15
I/ O14
7
A6
I/ O
2
8
A7
I/ O3
I/ O4
9
A8
I/ O
13
10
11
12
13
14
15
16
17
18
19
20
21
22
A12
A13
V
V
SS
CC
V
V
CC
SS
I/ O12
I/ O5
I/ O6
I/ O7
I/ O8
WE
A5
I/ O1–I/ O8
I/ O
Control circuit
I/ O11
I/ O10
I/ O9
CS2
buffer
I/ O9–I/ O16
Column decoder
WE
A14
A6
A13
A7
A12
A8
A11
A9
A10
UB
OE
LB
CS1
CS2
48-CSP Ball-Grid-Array Package
1
2
3
4
5
6
A
B
C
D
E
LB
OE
A
A
A
2
CS2
0
1
I/ O9 UB
A
A
CS1 I/ O1
I/ O2 I/ O3
I/ O4 VCC
3
4
I/ O10 I/ O11
A
A
6
5
V
I/ O12
A
A
7
SS
17
VCC I/ O13 NC
A
I/ O5
V
SS
16
F
I/ O15 I/ O14
I/ O16 NC
A
A
I/ O6 I/ O7
WE I/ O8
14
15
G
H
A
A
13
12
NC
A
A
A
A
11
NC
8
9
10
Selection guide
VCC Range
Power Dissipation
Typ2
(V)
Max
(V)
Speed
(ns)
Operating (ICC1
)
Standby (ISB2)
Min
(V)
Product
Max (mA)
Max (µA)
AS6UA25617
AS6UA25617
2.7
2.3
3.0
2.5
2.0
3.6
2.7
2.3
55
70
2
1
1
20
15
12
AS6UA25617*
1.65
100
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.