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AS6UA25616-100BI PDF预览

AS6UA25616-100BI

更新时间: 2024-10-31 20:04:11
品牌 Logo 应用领域
ALSC 静态存储器内存集成电路
页数 文件大小 规格书
9页 206K
描述
Standard SRAM, 256KX16, 100ns, CMOS, PBGA48, FBGA-48

AS6UA25616-100BI 数据手册

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Advance information  
June 2000  
AS6UA25616  
1.65V to 3.6V 256K×16 Intelliwatt™ low-power CMOS SRAM with one chip enable  
Low power consumption: STANDBY  
- 29 µW max at 3.6V  
‘Features  
AS6UA25616  
- 11 µW max at 2.7V  
• Intelliwatt™ active power circuitry  
• Industrial and commercial temperature ranges available  
• Organization: 262,144 words x 16 bits  
• 2.7V to 3.6V at 55 ns  
- 9 µW max at 2.3V  
• 1.2V data retention  
Equal access and cycle times  
Easy memory expansion with CS, OE inputs  
• 2.3V to 2.7V at 70 ns  
• 1.65V to 2.3V at 100 ns  
Smallest footprint packages  
- 48-ball FBGA  
Low power consumption: ACTIVE  
- 54 mW at 3.6V and 55 ns  
- 400-mil 44-pin TSOP II  
ESD protection 2000 volts  
Latch-up current 200 mA  
- 27 mW at 2.7V and 70 ns  
- 14 mW at 2.3 V and 100 ns  
Logic block diagram  
Pin arrangement (top view)  
44-pin 400-mil TSOP II  
A0  
A1  
A2  
V
A4  
A3  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A5  
DD  
2
A6  
A2  
3
A7  
256K × 16  
A3  
V
SS  
A1  
4
OE  
A4  
Array  
(4,194,304)  
A0  
5
UB  
A6  
CS  
6
LB  
A7  
A8  
I/ O15  
I/ O14  
I/ O13  
I/ O12  
I/ O0  
I/ O1  
I/ O2  
I/ O3  
7
8
A12  
A13  
9
10  
11  
12  
13  
14  
15  
16  
17  
V
V
CC  
SS  
CC  
I/ O0–I/ O7  
I/ O8–I/ O15  
I/ O  
Control circuit  
V
V
SS  
buffer  
I/ O4  
I/ O5  
I/ O6  
I/ O11  
I/ O10  
I/ O9  
I/ O8  
NC  
Column decoder  
WE  
I/ O  
7
WE  
A17  
A16  
A15  
A14  
A13  
1
8
A8  
19  
20  
21  
22  
A9  
A10  
A11  
A12  
UB  
OE  
LB  
CS  
Note: A “MODEpad is to be placed between pins 33 and 34 and 11 and 12,  
shorted. The bonding of this pad to V or V configures the device. There should  
CC SS  
only be 44+2+2 pads on the chip. Two extra V to separate out Array from  
CC  
Peripheral and Two-Mode Pads.  
48-CSP Ball-Grid-Array Package  
1
2
3
4
5
6
A
B
C
D
E
LB  
OE  
A0  
A3  
A1  
A4  
A2  
NC  
I/ O8 UB  
CS I/ O0  
I/ O9 I/ O10 A5  
VSS I/ O11 A17  
A6 I/ O1 I/ O2  
A7 I/ O3 VCC  
VCC I/ O12 NC A16 I/ O4 VSS  
I/ O14 I/ O13 A14 A15 I/ O5 I/ O6  
I/ O15 NC A12 A13 WE I/ O7  
F
G
H
NC  
A8  
A9  
A10 A11  
NC  
Selection guide  
VCC Range  
Power Dissipation  
Operating (ICC1  
)
Standby (ISB2)  
Min  
(V)  
Typ2  
(V)  
Max  
Speed  
(ns)  
Product  
(V)  
3.6  
2.7  
2.3  
Max (mA)  
Max (µA)  
AS6UA25616  
AS6UA25616  
AS6UA25616*  
2.7  
2.3  
3.0  
2.5  
2.0  
55  
70  
2
1
1
20  
15  
12  
1.65  
100  
6/ 19/ 00  
ALLIANCE SEMICONDUCTOR  
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.  

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