Datasheet > AS6C6264A-70SIN

AS6C6264A-70SIN

更新时间： 2024-09-14 01:06:31

品牌	Logo	应用领域
ALSC		ISM频段静态存储器光电二极管内存集成电路
页数	文件大小	规格书
10页	885K
描述
Common data inputs and outputs

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中文翻译

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数据手册
替代型号

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AS6C6264A-70SIN 数据手册

MARCH 2009

AS6C6264A

8K X 8 BIT LOW POWER CMOS SRAM

FEATURES

DESCRIPTION

data input and control signals W or

G, the operating current (at IO = 0

mA) drops to the value of the

operating current in the Standby

mode. The Read cycle is finished by

the falling edge of E2 or W, or by

the rising edge of E1, respectively.



8192 x 8 bit static CMOS RAM

The AS6C6264A is a static RAM

manufactured using a CMOS

process technology with the

following operating modes:

- Read - Standby

- Write - Data Retention

The memory array is based on a 6-

transistor cell.

70 ns Access Times

Common data inputs and

outputs

Three-state outputs

Typ. operating supply current



70 ns: 10 mA



Standby current:

Data retention is guaranteed down

to 2 V. With the exception of E2, all

inputs consist of NOR gates, so that

no pull-up/pull-down resistors are

required. This gate circuit allows to

achieve low power standby

< 2 μA at Ta ≤ 70 °C

The circuit is activated by the rising

edge of E2 (at E1 = L), or the falling

edge of E1 (at E2 = H). The address

and control inputs open

Data retention current at 2 V:

< 1 μA at Ta ≤ 70 °C



TTL/CMOS-compatible

Automatic reduction of power

dissipation in long Read or Write

cycles

Power supply voltage 5 V

Operating temperature ranges:

simultaneously. According to the

information of W and G, the data

inputs, or outputs, are active. In a

Read cycle, the data outputs are

activated by the falling edge of G,

afterwards the data word read will

be available at the outputs DQ0 -

DQ7. After the address change, the

data outputs go High-Z until the new

read information is available. The

data outputs have no preferred

state. If the memory is driven by

CMOS levels in the active state, and

if there is no change of the address,

requirements by activation with TTL-

levels too.



If the circuit is inactivated by E2 = L,

the standby current

0 to 70 °C

-40 to 85 °C



ESD protection > 2000 V

(MIL STD 883C M3015.7)

Latch-up immunity > 100 mA

Packages: PDIP28 (600 mil)

SOP28 (330 mil)



PIN CONFIGURATION

PIN DESCRIPTION

MARCH/2009

ALLIANCE MEMORY

PAGE 1 of 10

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中文翻译

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AS6C6264A-70SIN 替代型号

型号	品牌	替代类型	描述	数据表
AS6C6264A-70SCN	ALSC	完全替代	Common data inputs and outputs
AS6C4008-55PCN	ALSC	功能相似	512K X 8 BIT LOW POWER 512K X 8 BIT LOW POWER CMOS SRAM

与AS6C6264A-70SIN相关器件

型号	品牌	获取价格	描述	数据表
AS6C8008	ALSC	获取价格	512K X 8 BIT LOW POWER 1024K X 8 BIT SUPER LOW POWER CMOS SRAM
AS6C8008-55ZIN	ALSC	获取价格	512K X 8 BIT LOW POWER 1024K X 8 BIT SUPER LOW POWER CMOS SRAM
AS6C8008A	ALSC	获取价格	Power Supply Voltage
AS6C8008A-45BIN	ALSC	获取价格	Power Supply Voltage
AS6C8008A-45ZIN	ALSC	获取价格	Power Supply Voltage
AS6C8016	ALSC	获取价格	Fully static operation
AS6C8016-55BIN	ALSC	获取价格	512K X 16 BIT SUPER LOW POWER CMOS SRAM
AS6C8016-55ZIN	ALSC	获取价格	512K X 16 BIT SUPER LOW POWER CMOS SRAM
AS6C8016A	ALSC	获取价格	Process Technology
AS6C8016A-55BIN	ALSC	获取价格	Process Technology

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