Datasheet > AS6C62256A-70PIN

AS6C62256A-70PIN

更新时间： 2024-09-14 01:23:31

品牌	Logo	应用领域
ALSC		ISM频段静态存储器光电二极管内存集成电路
页数	文件大小	规格书
10页	599K
描述
32K X 8 BIT LOW POWER CMOS SRAM

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中文翻译

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数据手册

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AS6C62256A-70PIN 数据手册

APRIL 2009

AS6C62256A

32K X 8 BIT LOW POWER CMOS SRAM

FEATURES

DESCRIPTION

The Read cycle is finished by the

falling edge of W, or by the rising

edge of E, respectively.



32768x8 bit static CMOS RAM

The AS6C62256A is a static RAM

manufactured using a CMOS

process technology with the

following operating modes:

Access times 70 ns

Common data inputs and data

outputs

Three-state outputs

Typ. operating supply current

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so that

no pull-up/pull-down resistors are

required.

- Read

- Write

- Standby

- Data Retention



The memory array is based on a 6-

transistor cell.

70 ns: 50 mA



TTL/CMOS-compatible

Automatical reduction of power

dissipation in long Read Cycles

Power supply voltage 5V + 10%

Operating temperature ranges

The circuit is activated by the falling

edge of E. The address and control

inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the data

outputs are activated by the falling

edge of G, afterwards the data word

read will be available at the outputs

DQ0-DQ7. After the address



0 to 70 °C

-40 to 85 °C



QS 9000 Quality Standard

ESD protection > 2000 V

(MIL STD 883C M3015.7)

Latch-up immunity >100 mA

Packages: PDIP28 (600 mil)

SOP28 (330 mil)



change, the data outputs go High-Z

until the new information read is

available. The data outputs have not

preferred state.

PIN CONFIGURATION

PIN DESCRIPTION

APRIL/2009

ALLIANCE MEMORY

PAGE 1 of 10

12 3 4 5 6 7...10

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