Datasheet > AS5SS128K36DQC-7.5L/ET

AS5SS128K36DQC-7.5L/ET

更新时间： 2024-11-08 04:04:11

品牌	Logo	应用领域
MICROSS		静态存储器
页数	文件大小	规格书
20页	344K
描述
Standard SRAM

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中文翻译

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数据手册

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SSRAM

AS5SS128K36

128K x 36 4Mb FLOW THROUGH ‘NO WAIT’

STATE BUS SYNCHRONOUS SRAM

FEATURES

• Available in Mil-Temp*, Enhanced* & Industrial Ranges

• 100 percent bus utilization

• No wait cycles between Read and Write¹

• Internal self-timed write cycle

• Individual Byte Write Control

GENERAL DESCRIPTION

TheAS5SS128K36 is a high-speed, low-power synchronous

static RAM designed to provide a burstable, high-performance,

“no wait” state device for networking and communication ap-

plications. It is organized as 128K words by 36 bits fabricated

with Micross’ advanced CMOS technology.

• Single Read / Write control pin

• Clock controlled, registered address, data and

control

• Interleaved or linear burst sequence control using

MODE input

Incorporating a ‘no wait’state feature, wait cycles are eliminated

when the bus switches from read to write, or write to read.

This device integrates a 2-bit burst counter, high-speed SRAM

core, and high-drive capability outputs into a single monolithic

circuit.

• Three chip enables for simple depth expansion

and address pipelining

• Power down mode

• Common data inputs and data outputs

• CKE\ pin to enable clock and suspend operation

• Power Supply: V_DD3.3V ± 5%, V_DDQ3.3V/2.5V ± 5%

• JEDEC 100-Pin TQFP

• TQFP in copper lead frame for superior thermal

performance

All synchronous inputs pass through registers are controlled by

a positive-edge-triggered single clock input. Operations may

be suspended and all synchronous inputs ignored when Clock

Enable, CKE\ is HIGH. In this state the internal device will hold

their previous values.

All Read, Write and Deselect cycles are initiated by the ADV

input. When the ADV is HIGH the internal burst counter is

incremented. New external addresses can be loaded when

ADV is LOW.

• RoHs compliant options available

Write cycles are internally self-timed and are initiated by the

rising edge of the clock inputs and when WE\ is LOW. Separate

byte enables allow individual bytes to be written. A burst mode

pin (MODE) deﬁnes the order of the burst sequence. When tied

HIGH, the interleaved burst sequence is selected. When tied

LOW, the linear burst sequence is selected.

*Consult factory for /XT and /ET products.

FAST ACCESS TIME

Symbol

Parameter

ClockꢀAccessꢀTime

CycleꢀTime

Ͳ7.5

7.5

Ͳ8.5

8.0

Units

t_KQ

t_KC

8.5

f_MAX

Frequency

117

100

MHz

NOTE 1: Otherwise known as (ZBL) Zero Bus Latency.

For more products and information

please visit our web site at

www.micross.com

Micross Components reserves the right to change products or speciﬁcations without notice.

AS5SS128K36

Rev. 2.8 09/11

12 3 4 5 6 7...20

中文翻译

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与AS5SS128K36DQC-7.5L/ET相关器件

型号	品牌	获取价格	描述	数据表
AS5SS128K36DQC-7.5L/IT	MICROSS	获取价格	Standard SRAM
AS5SS128K36DQC-7.5L/XT	MICROSS	获取价格	Standard SRAM
AS5SS128K36DQC-8/ET	MICROSS	获取价格	Standard SRAM
AS5SS128K36DQC-8/IT	MICROSS	获取价格	Standard SRAM
AS5SS128K36DQC-8/XT	MICROSS	获取价格	Standard SRAM
AS5SS128K36DQC-8L/ET	MICROSS	获取价格	Standard SRAM
AS5SS128K36DQC-8L/IT	MICROSS	获取价格	Standard SRAM
AS5SS128K36DQC-8L/XT	MICROSS	获取价格	Standard SRAM
AS5SS128K36DQCR-7.5L/ET	MICROSS	获取价格	Standard SRAM
AS5SS128K36DQCR-7.5L/IT	MICROSS	获取价格	Standard SRAM

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