Datasheet > AS4CM4EOQ

AS4CM4EOQ

更新时间： 2024-11-24 06:37:51

品牌	Logo	应用领域
ALSC		动态存储器
页数	文件大小	规格书
16页	354K
描述
4M X 4 CMOS Quad CAS DRAM (EDO) family

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中文翻译

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数据手册

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AS4CM4EOQ 数据手册

March 2001

AS4C4M4EOQ

AS4C4M4E1Q

4M ✕ 4 CMOS QuadCAS DRAM (EDO) family

Features

• Organization: 4,194,304 words × 4 bits

AS4C4M4E1Q

• High speed

- RAS-only and hidden refresh or CAS-before-RAS refresh

or self-refresh

• TTL-compatible

• 4 separate CAS pins allow for separate I/O operation

• JEDEC standard package

- 50/60 ns RAS access time

- 25/30 ns column address access time

- 12/15 ns CAS access time

• Low power consumption

- Active: 495 mW max

- 300 mil, 28-pin SOJ

- Standby: 5.5 mW max, CMOS I/O

• Extended data out

- 300 mil, 28-pin TSOP

• 5V power supply

• Refresh

• Latch-up current ≥ 200 mA

• ESD protection ≥ 2000 mV

- 4096 refresh cycles, 64 ms refresh interval for

4C4M4EOQ

- 2048 refresh cycles, 32 ms refresh interval for

Pin arrangement

Pin designation

Pin(s)

A0 to A11

RAS

Description

SOJ

TSOP

Address inputs

Row address strobe

Column address strobe

Write enable

Input/output

Output enable

Power

V_CC

GND

I/O3

I/O2

CAS3

CAS2

V_CC

GND

I/O3

I/O2

CAS3

I/O0

I/O1

I/O0

I/O1

CAS

RAS

*NC/A11

CAS0

*NC/A11

CAS0

CAS2

GND

CAS1

A10

CAS1

A10

I/O0 to I/O3

V_CC

GND

Ground

No Connection

* NC on 2K refresh version; A11 on 4K refresh version

Selection guide

Symbol

t_RAC

t_CAA

t_CAC

t_OEA

t_RC

4C4M4EOQ/E1Q-50

4C4M4EOQ/E1-60

Unit

Maximum RAS access time

110

1.0

Maximum column address access time

Maximum CAS access time

Maximum output enable (OE) access time

Minimum read or write cycle time

Minimum hyper page mode cycle time

Maximum operating current

100

t_PC

I_CC1

I_CC5

100

1.0

Maximum CMOS standby current

3/22/01; v.1.0

Alliance Semiconductor

P. 1 of 16

12 3 4 5 6 7...16

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