Datasheet > 存储 > DRAM> AS4C4M4F1-60TI

AS4C4M4F1-60TI

更新时间： 2024-11-24 06:37:51

品牌	Logo	应用领域
ALSC		存储内存集成电路光电二极管动态存储器
页数	文件大小	规格书
18页	271K
描述
5V 4M×4 CMOS DRAM (Fast Page mode)

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中文翻译

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数据手册

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AS4C4M4F1-60TI 数据手册

AS4C4M4F0

AS4C4M4F1

5V 4M×4 CMOS DRAM (Fast Page mode)

Features

• Organization: 4,194,304 words × 4 bits

• High speed

• TTL-compatible, three-state I/O

• JEDEC standard package

- 300 mil, 24/26-pin SOJ

- 300 mil, 24/26-pin TSOP

• Latch-up current ≥ 200 mA

• ESD protection ≥ 2000 mV

- 50/60 ns RAS access time

- 25/30 ns column address access time

- 12/15 ns CAS access time

• Low power consumption

- Active: 908 mW max

- Standby: 5.5 mW max, CMOS I/O

• Fast page mode

• Industrial and commercial temperature available

• Refresh

- 4096 refresh cycles, 64 ms refresh interval for

AS4C4M4F0

- 2048 refresh cycles, 32 ms refresh interval for

AS4C4M4F1

- RAS-only or CAS-before-RAS refresh or self-refresh

Pin arrangement

Pin designation

Pin(s)

A0 to A11

RAS

Description

SOJ

TSOP

Address inputs

Row address strobe

Column address strobe

Write enable

Input/output

Output enable

Power

V_CC

GND

I/O3

I/O2

CAS

V_CC

GND

I/O3

I/O2

CAS

I/O0

I/O1

I/O0

I/O1

CAS

RAS

*NC/A11

A10

GND

I/O0 to I/O3

V_CC

GND

Ground

*NC on 2K refresh version; A11 on 4K refresh version

Selection guide

AS4C4M4F0-50

AS4C4M4F1-50

AS4C4M4F0-60

AS4C4M4F1-60

Symbol

Unit

Maximum RAS access time

t_RAC

t_CAA

t_CAC

t_OEA

t_RC

135

1.0

Maximum column address access time

Maximum CAS access time

Maximum output enable (OE) access time

Minimum read or write cycle time

Minimum fast page mode cycle time

Maximum operating current

100

t_PC

I_CC1

I_CC5

120

1.0

Maximum CMOS standby current

4/11/01; v.0.9

Alliance Semiconductor

P. 1 of 18

12 3 4 5 6 7...18

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