ꢓꢔꢐꢕꢖꢗꢘꢑꢑ
ꢀꢁꢂꢃꢄꢅꢄꢆꢇꢁꢈꢉꢊꢆꢋꢌꢁꢅꢇꢍꢄꢌꢆ
ꢎꢏꢃꢈꢉꢐꢑꢑꢒ
&
ꢙꢗꢉꢚꢒꢐꢛꢉꢜꢉꢝ ꢐꢚ!ꢛꢉꢞꢉꢒ!ꢉ#$%ꢔꢉꢟꢃꢇ'(ꢉ))ꢀ*%$
ꢟꢂꢇꢍꢏꢁꢂ'
• Organization: 512Kx8/ 256Kx16
• Sector architecture
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
- One 16K; two 8K; one 32K; and seven 64K byte sectors
- One 8K; two 4K; one 16K; and seven 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/ write operations
• Sector protection
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO; availability TBD
- 48-pin BGA
• Detection of program/ erase cycle completion
- DQ7 DATA polling
• High speed 70/ 80/ 90/ 120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/ verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/ erases chip or specified
sectors
- DQ6 toggle bit
- DQ2 toggle bit
- RY/ BY output
• Erase suspend/ resume
- Supports reading data from or programming data
to a sector not being erased
• Hardware RESET pin
• Low V write lock-out below 1.5V
CC
- Resets internal state machine to read mode
• Low power consumption
• 10 year data retention at 150C
• 100,000 write/ erase cycle endurance
ꢖꢌ-ꢄ+ꢉ.ꢃꢌ+/ꢉ,ꢄꢇ-ꢁꢇꢅ
Sector protect/
erase voltage
switches
RY/ BY
DQ0–DQ15
V
CC
V
SS
Erase voltage
generator
Input/ output
buffers
RESET
Program/ erase
control
WE
BYTE
Program voltage
generator
Command
register
STB
Chip enable
Output enable
Logic
Data latch
CE
OE
A-1
Y decoder
Y gating
STB
V
detector
Timer
CC
X decoder
Cell matrix
A0–A17
ꢔꢂꢃꢂ+ꢍꢄꢌꢆꢉ-ꢏꢄ,ꢂ
29LV400-70
29LV400-80
29LV400-90
29LV400-120
Unit
ns
Maximum access time
t
70
70
30
80
80
30
90
90
35
120
120
50
AA
Maximum chip enable access time
Maximum output enable access time
t
ns
CE
t
ns
OE
8/ 9/ 01; V.0.9.9.1
ꢓꢃꢃꢄꢇꢆ+ꢂꢉꢔꢂꢅꢄ+ꢌꢆ,ꢏ+ꢍꢌꢁ
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