ꢀꢕꢆꢖꢗꢘꢈꢙꢇ
ꢀꢁꢂꢁꢃꢄꢅꢆꢇꢇꢈ
ꢀꢉꢊꢋꢌꢍꢎꢉꢅꢏꢌꢐꢑꢒꢓꢋꢄꢔꢑꢌ
&
ꢚꢘꢅꢆꢛꢅꢜꢅꢝꢅ ꢅꢈꢛꢅꢜꢅꢈꢙꢅ!ꢅ"ꢛ#ꢕꢅ$%ꢋꢃꢞꢅ''()#ꢛ
$ꢎꢋꢄꢁꢒꢎꢃ
• Organization: 2M×8 / 1M×16
• Sector architecture
• Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO (availability TBD)
• CFI (Common Flash Interface) compliant
• Detection of program/ erase cycle completion
- DQ7 DATApolling
- DQ6 toggle bit
- RY/ BYoutput
- One 16K; two 8K; one 32K; and thirty-one 64K byte sectors
- One 8K; two 4K; one 16K; and thirty-one 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/ write operations
• Sector protection
• High speed 70/ 80/ 90/ 120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/ verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/ erases chip or specified
sectors
• Erase suspend/ resume
- Supports reading data from or programming data to a
sector not being erased
• Hardware RESET pin
- Resets internal state machine to read mode
• Low V write lock-out below 1.5V
CC
• 10 year data retention at 150C
• 100,000 write/ erase cycle endurance
ꢗꢑꢂꢔꢍꢅ*%ꢑꢍ+ꢅꢉꢔꢋꢂꢒꢋꢓ
(ꢔꢌꢅꢋꢒꢒꢋꢌꢂꢎꢓꢎꢌꢄ
48-pin TSOP
44-pin SO
Sector protect/
erase voltage
RY/ BY
DQ0–DQ15 (A-1)
switches
V
CC
Reset
A18
A17
A7
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WE
A19
A8
V
2
SS
Erase voltage
generator
Input/ output
buffers
3
RESET
4
A9
A6
5
A10
A11
A12
A13
A14
A15
A16
BYTE
Program/ erase
control
A5
6
WE
A4
7
BYTE
A3
8
Program voltage
generator
A2
9
Command
register
ꢊꢐꢗꢘꢙꢚꢛꢜꢝ
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
STB
Chip enable
Output enable
Logic
Data latch
CE
CE
OE
V
V
SS
SS
OE
DQ0
DQ15/ A-1
DQ7
DQ8
DQ14
DQ6
Y decoder
Y gating
DQ1
STB
DQ9
DQ13
DQ5
DQ2
V
detector
Timer
CC
DQ10
DQ3
DQ12
DQ4
X decoder
Cell matrix
DQ11
VCC
A0–A19
ꢕꢎ%ꢎꢍꢄꢔꢑꢌꢅꢂꢁꢔꢉꢎ
29LV160-70
29LV160-80 29LV160-90 29LV160-120
Unit
Maximum access time
Maximum chip enable access time
Maximum output enable access time
t
70
70
30
80
80
30
90
90
35
120
120
50
ns
ns
ns
AA
t
CE
t
OE
8/ 30/ 01; V.0.9.5
ꢀ%%ꢔꢋꢌꢍꢎꢅꢕꢎꢓꢔꢍꢑꢌꢉꢁꢍꢄꢑꢒ
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