Datasheet > ARM966E-S?(CW001105)

ARM966E-S?(CW001105)

更新时间： 2024-11-25 23:31:11

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ARM966E-S?(CW001105)

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ARM966E-S?(CW001105) 数据手册

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CW001105 - 200 MHz

™

Synthesized ARM966E-S Core

O V E R V I E W

F E A T U R E S A N D B E N E F I T S

• 200 MHz Operating frequency

The CW001105 processor core is a 200 MHz implementation of the popular

ARM966E-S™, synthesized onto LSI Logic’s G12P 0.18 micron high performance

process technology.

T =115 ^oC, V

=1.8 V, slow process

• Implemented on LSI Logic’s G12P

0.18 micron, 1.8 V process

The ARM966E-S, which is based on the five stage pipeline ARM9E-S™

Harvard architecture processor, also contains a complete memory subsystem of

tightly coupled instruction and data RAMs, an Embedded Trace Macrocell

(ETM) interface, and an AMBA™ (Advanced Microprocessor Bus Architecture)

AHB (Advanced High performance Bus) interface unit. This high level of inte-

gration helps ease the task of integrating the core into your System on Chip

(SoC) design. Tight coupling of the RAM allows for high speed operation and

predictable memory timing. This makes the core an ideal choice for real time

systems needing timing critical execution. The instruction and data RAM sizes

are user configurable up to 512 KBytes. The AHB interface includes a write

buffer capable of burst transfers and split transactions. The ETM interface, when

used with the optional ETM core, provides extensive real-time trace capabilities.

• 0.9mW/MHz power dissipation,

(excluding memories)

• ARM966E-S Industry Standard

Architecture

• Fully configurable memory subsystem

for maximum flexibility

• Synthesized core for optimal timing

accuracy and ASIC compatible

design flow

• Complete AMBA subsystem

reference design available

• Extensive portfolio of AMBA

peripherals

ETM (Embedded Trace Macrocell)

RAM Control

• Regional ARM CoreWare design

support

Instruction

RAM

ARM9E-S

Data RAM

System

Controller

Write Buffer and AHB Interface

The

™

Communications

Company

ARM966E-S Block Diagram

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