Datasheet > ARM946E-S?(CW001100)

ARM946E-S?(CW001100)

更新时间： 2024-11-25 23:31:11

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
2页	147K
描述
ARM946E-S?(CW001100)

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ARM946E-S?(CW001100) 数据手册

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CW001100 - 200 MHz Synthesized

™

ARM946E-S Core with Cache Memories

O V E R V I E W

F E A T U R E S A N D B E N E F I T S

• 200 MHz operating frequency

(worst case commercial conditions)

The CW001100 processor core is a 200 MHz implementation of the popu-

lar ARM946E-S™, synthesized onto LSI Logic’s G12P 0.18 micron high perfor-

mance process technology.

• Implemented on LSI Logic’s G12P

0.18 micron, 1.8 V process

™

The ARM946E-S, which is based on the five stage pipeline ARM9E-S

• 1.9 mW/MHz power dissipation,

(with 0 kBytes TCMs)

Harvard architecture processor, also contains a complete memory subsystem of

instruction and data caches (16 kBytes each), and configurable tightly coupled

instruction and data memories (TCMs). The core also includes an Embedded

• ARM946E-S industry standard

architecture

™

Trace Macrocell (ETM) interface, and an AMBA (Advanced Microprocessor

• 16 kByte instruction and data

caches (4-way set associative)

Bus Architecture) AHB (Advanced High performance Bus) interface unit. This

high level of integration helps ease the task of integrating the core into your

System-on-Chip (SoC) design.

• Configurable TCMs

• Synthesized core for optimal timing

accuracy and ASIC compatible

design flow

• Regional ARM CoreWare design

support

The

Communications

Company

ARM946E-S Block Diagram

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