Preliminary Datasheet
3A DDR TERMINATION REGULATOR
AP2302
General Description
Features
·
Support Both DDR I (1.25V ) and DDR II
TT
The AP2302 linear regulator is designed to meet the
JEDEC specification SSTL-2 and SSTL-18 for termi-
nation of DDR-SDRAM. The regulator can sink or
source up to 3A current continuously, offers enough
current for most DDR applications. Output voltage is
designed to track the reference voltage within a 2%
(DDR I) and 3% (DDR II) tolerance for load regulation
while preventing shooting through on the output stage.
On-chip thermal limiting provides protection against a
combination of high current and ambient temperature
which would create an excessive junction temperature.
(0.9V ) Requirements
TT
·
·
·
Source and Sink Current up to 3A
High Accuracy Output Voltage at Full-load
Adjustable V
by External Resistors
OUT
·
Shutdown for Standby or Suspend Mode
Operation with High-impedance Output
Applications
The AP2302, used in conjunction with series termina-
tion resistors, provides an excellent voltage source for
active termination schemes of high speed transmission
lines as those seen in high speed memory buses and
distributed backplane designs.
·
·
·
DDR-SDRAM Termination
DDR-II Termination
SSTL-2 Termination
The AP2302 is available in SOIC-8, TO-252-5L and
TO-263-5L packages.
TO-252-5L
SOIC-8
TO-263-5L
Figure 1. Package Types of AP2302
Jul. 2006 Rev. 1. 2
BCD Semiconductor Manufacturing Limited
1