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AN87C196LA PDF预览

AN87C196LA

更新时间: 2024-11-27 22:39:11
品牌 Logo 应用领域
英特尔 - INTEL 微控制器和处理器
页数 文件大小 规格书
21页 291K
描述
CHMOS 16-BIT MICROCONTROLLER

AN87C196LA 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:LCC包装说明:QCCJ, LDCC52,.8SQ
针数:52Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.69
Is Samacsys:NBase Number Matches:1

AN87C196LA 数据手册

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PRODUCT PREVIEW  
87C196LA  
CHMOS 16-BIT MICROCONTROLLER  
Automotive  
20 MHz operation†  
Full-duplex serial I/O port with  
dedicated baud-rate generator  
24 Kbytes of on-chip OTPROM  
768 bytes of on-chip register RAM  
Register-to-register architecture  
Enhanced full-duplex, synchronous  
serial I/O port (SSIO)  
Programmable 8- or 16-bit external bus  
Peripheral transaction server (PTS)  
with high-speed, microcoded interrupt  
service routines  
Optional clock doubler with  
programmable clock output signal  
SFR register that indicates the source  
Six-channel/10-bit A/D with sample and  
of the last reset  
hold  
Design enhancements for EMI  
High-speed event processor array  
— Six capture/compare channels  
— Two compare-only channels  
— Two 16-bit software timers  
reduction  
Oscillator failure detection circuitry  
Watchdog timer (WDT)  
40° C to +125° C ambient temperature  
52-pin PLCC package  
16 MHz standard; 20 MHz is speed premium  
NOTE  
This datasheet contains information on products in the design phase of development.  
The specifications are subject to change without notice. Verify with your local Intel sales  
office that you have the latest datasheet before finalizing a design.  
The 87C196LA is a high-performance 16-bit microcontroller. The 87C196LA is composed of a high-speed  
core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a  
dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave  
transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with  
prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture  
and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophis-  
ticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock  
doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock  
speed as a more costly 8 MHz resonator in previous applications. This same circuitry can drive other devices  
where a separate resonator was required in the past. Another cost-savings feature is the fact that the I/O  
ports are driven low at reset, avoiding the need for pull-up resistors.  
COPYRIGHT © INTEL CORPORATION, 1996  
October 1996  
Order Number: 272806-001  

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