Serial EEPROM Endurance
AN537
Everything a System Engineer Needs to Know About Serial EEPROM Endurance
The term “endurance” has become a confusing param-
eter for both users and manufacturers of EEPROM
products. This is largely because many semiconductor
EEPROM MEMORY CELL
OPERATION AND
CHARACTERISTICS
vendors treat this important application-dependent reli-
ability parameter as a vague specmanship topic. As a
result, the system engineer often designs without proper
reliability information or under-utilizes the EEPROM as
an effective solution.
In discussing endurance characteristics of EEPROMs,
it’s important to review how these components operate,
and why and how they fail. Figure 1 illustrates a CMOS
floating gate EEPROM cell, including voltage conditions
for READ, ERASE, and WRITE operations. To erase or
write, the row select transistor must have the relatively
high potential of 20V. This voltage is internally gener-
ated on chip by a charge pump, with the only external
voltage required being VDD. The only difference be-
tween an ERASE and a WRITE is the direction of the
applied field potential relative to the polysilicon floating
gate.
Endurance(thenumberoftimesanEEPROMcellcanbe
erased and rewritten without corrupting data) is a mea-
sure of the device’s reliability, not its parametric perfor-
mance. As such, endurance is not achieved by some-
howmakingEEPROMdevicesmoredurableorrobustto
extendthelifeoftheintrinsicerase/writecycle, butrather
by reducing their defect-density failure rates. This has a
direct impact on the design engineer characterizing
EEPROM memory needs for an application and evaluat-
ing components from various manufacturers. The sys-
tem design engineer needs to understand not only the
relationship between the application, expected use and
failure mechanisms, but also how the manufacturer has
arrived at published endurance data for its components.
When 20V is applied to the polysilicon memory cell gate
and 0V is applied to the bit line drain (column), electrons
tunnel from the substrate through the 90-angstrom Tun-
nel Dielectric (TD) oxide to the polysilicon floating gate
untilthepolysiliconfloatinggateissaturatedwithcharge.
The cell is now at an ERASE state of “1”. When 0V is
applied to the polysilicon memory cell gate and 20V is
applied to the bit line drain (column), electrons tunnel
from the polysilicon floating gate through the TD oxide to
the substrate. The cell then is at a WRITE state of “0”.
This sequence of the transfer of charge onto the floating
gate (ERASE) and the electrical removal of that charge
from the floating gate (WRITE) is one ERASE/ WRITE
cycle, or “E/W cycle.”
This tutorial volume is intended to clarify some of the
issues in the industry and provide a tool for the system
design engineer, the system reliability engineer, and the
component engineer to determine EEPROM reliability
and understanding how to apply it to actual application
requirements. It will examine four main areas:
•
CMOS floating gate memory cell operation and char-
acteristics
The field (applied voltage to an oxide thickness) across
the tunneling path created by the 20V potential is ex-
tremely high in order to transfer the electrons. Over the
cell’s“applicationtime,”asmeasuredbyE/Wcycles, the
EEPROM cell begins to wear out due to the field stress.
The EEPROM cell wears out as the number of cycles
increase resulting in the voltage margin between the
ERASE and WRITE states decreasing until finally there
is not enough margin for the EEPROM sense amp to
detect a difference in the two states during a READ.
Failure is defined as when the sense amp can no longer
reliably differentiate logic state changes.
•
Significant process and design interactions and en-
durance characterization variables
8
•
•
Common misinterpretations of endurance
Determining some real world application reliability
requirements
Figure 2 (single cell EEPROM endurance characteris-
tics) illustrates that the intrinsic wear out point for a
normal cell with specified dimensions and electrical
characteristics is very acceptable, in excess of 2 million
E/W cycles. Failures at lower cycles are due mostly to
very small defects or imperfections in the oxide or
silicon-to-oxide interface.
© 1992 Microchip Technology Inc.
DS00537A-page 1
8-15
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