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AN535

更新时间： 2024-11-14 22:39:11
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摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
12页 344K
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PHASE LOCKED LOOP DESIGN FUNDAMENTALS

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Freescale Semiconductor, Inc.  
Order this document  
by AN535/D  
SEMICONDUCTOR APPLICATION NOTE  
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Prepared by: Garth Nash  
Applications Engineering  
The parameters in Figure 1 are defined and will be used  
throughout the text.  
ABSTRACT  
The fundamental design concepts for phase-locked loops  
implemented with integrated circuits are outlined. The  
necessary equations required to evaluate the basic loop  
performance are given in conjunction with a brief design  
example.  
+
θ (s)  
e
θ (s)  
i
G(s)  
H(s)  
θ (s)  
o
–
INTRODUCTION  
The purpose of this application note is to provide the  
electronic system designer with the necessary tools to design  
and evaluate Phase-Locked Loops (PLL) configured with  
integrated circuits. The majority of all PLL design problems  
can be approached using the Laplace Transform technique.  
Therefore, a brief review of Laplace is included to establish a  
common reference with the reader. Since the scope of this  
article is practical in nature all theoretical derivations have  
been omitted, hoping to simplify and clarify the content. A  
bibliography is included for those who desire to pursue the  
theoretical aspect.  
θ (s) Phase Input  
i
θ (s) Phase Error  
e
θ (s) Output Phase  
o
G(s) Product of the Individual Feed  
Forward Transfer Functions  
H(s) Product of the Individual Feedback  
Transfer Functions  
Figure 1. Feedback System  
Using servo theory, the following relationships can be  
obtained.2  
PARAMETER DEFINITION  
The Laplace Transform permits the representation of the  
time response f(t) of a system in the complex domain F(s).  
This response is twofold in nature in that it contains both  
transient and steady state solutions. Thus, all operating  
conditions are considered and evaluated. The Laplace  
transform is valid only for positive real time linear parameters;  
thus, its use must be justified for the PLL which includes both  
linear and nonlinear functions. This justification is presented  
in Chapter Three of Phase Lock Techniques by Gardner.1  
1
q (s) +  
q (s)  
e
i
( 1 )  
( 2 )  
1 ) G(s) H(s)  
G(s)  
1 ) G(s) H(s)  
q (s) +  
o
q (s)  
i
These parameters relate to the functions of a PLL as shown  
in Figure 2.  
θ (s)  
i
θ (s)  
e
θ (s)  
o
f
i
Phase Detector  
Filter  
VCO/VCM  
f
o
f
N
o
θ (s)/N  
o
Programmable  
Counter (÷N)  
Figure 2. Phase Locked Loop  
REV 0  
Motorola, Inc. 1994  
For More Information On This Product,  
Go to: www.freescale.com  
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