Application Note
AN3004
Programming Guide, Integer N PLL Synthesizer
100 - 2800 MHz
Rev. V2
Programming Overview
Introduction
The programmable dividers and counters are serially
programmed using a standard 3-wire CMOS or TTL
interface. The programming data is input using the
Clock, Data and Load Enable input pins. The Clock
input latches one bit on the Data input into the PLL
shift register on the rising edge of each clock pulse
(MSB first). When the Load Enable input is HIGH the
stored data is transferred into the latches. The last
two bits are the control bits. The data is transferred
into the counters as shown below.
M/A-COM’s surface mount frequency synthesizers
integrate a low-noise buffered VCO, phase locked
loop circuit and low-pass loop filter. The VCO output
is coupled into the PLL circuit where the VCO
frequency is divided down in a dual-modulus
prescaler and 18-bit N Counter or feedback divider
(5-bit swallow counter and 13-bit programmable
divider) to the phase comparison frequency or step
size of the PLL. This is usually in the range of 10
kHz to 5 MHz for most applications. The prescaler
modulus is 32/33. The external reference oscillator
is also divided down in the 14-bit programmable R
Counter or reference divider to the same phase
comparison frequency.
Control
Data location
C2
0
C1
0
R Counter
N Counter
0
1
The divided VCO and divided reference signals are
then fed into the phase comparator, which produces
an error signal whose magnitude is proportional to
the phase difference between the two signals. The
error signal is then passed through a loop filter to
produce the desired performance characteristics and
the result is a voltage, which is applied to the tuning
input of the VCO. The frequency of the VCO is then
steered to the desired frequency, at which point the
phase difference in the phase comparator will be
zero. The phases of the divided VCO and the
divided reference signals are then said to be ‘locked’
to one another, hence the term phase locked loop.
1
0
Function Latch
Initialization
1
1
Programming the Reference Word
(R Counter)
If the control bits are (C2, C1) = (0, 0), data is
transferred from the 21-bit shift register into a latch
that sets the 14-bit R Counter. Bits R1 – R14 hold
the reference division ratio. Bits R15 – R18 are for
test modes, and should be set to 0 for normal use.
Bit R19 specifies lock detect (LD) precision and is
used in the digital lock detect mode, as described
in the Function Latch section. Serial data format is
shown on the next page, together with the pro-
gramming table for the R Counter.
Any subsequent phase or frequency perturbation on
the VCO output results in an error signal at the
output of the phase comparator. This error signal in
turn produces a modification of the tuning voltage to
maintain the phase locked condition. A typical
synthesizer block diagram is shown below.
Ref
Osc.
14-Bit
R Counter
Phase
Comparator
Loop
Filter
Clock
18-Bit
Function
Latch
21-Bit
Shfit Register
Latch Enable
Data
Output
VCO
Prescaler
32/33
18-Bit
N Counter
Typical Block Diagram
1
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Visit www.macomtech.com for additional data sheets and product information.
M/A-COM Technology Solutions Inc. and its affiliates reserve the right to make
changes to the product(s) or information contained herein without notice.
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