Preliminary
AN1024
GSI ECCRAMsTM
The Benefits of On-Chip ECC
The ECC implementation is entirely transparent to the user.
Type II and II+ ECCRAMs are fully compatible with other
Type II and II+ SigmaQuad and SigmaDDR SRAMs, except
with respect to Byte Write support. See Byte Write
Implications below for further information.
Introduction
Error Correction Code, or ECC, is commonly utilized with
SRAMs in applications where data corruption via SER events
is not easily tolerated. Typically, the ECC algorithms detect
and correct single-bit data errors. In some instances they can
also detect multi-bit errors, depending on the type of algorithm
used and the number of parity bits allocated to ECC.
Applications
The primary applications for ECCRAMs are those that demand
a very high level of dependability, such as military and other
data-critical applications, as well as those that are more
susceptible to SER events, such as aerospace, satellite, and
other applications expected to be utilized at high-altitude.
Traditionally, in environments that require high data integrity,
the ECC error detection and correction algorithms have been
implemented in custom ASIC- and FPGA-based memory
controllers. However, it has become increasingly rare for such
controllers to be designed in-house, due to cost, resource, and
time-to-market constraints. Unfortunately, the availability of
3rd party, off-the-shelf SRAM controllers designed for the
commercial market is quite limited, and those that are available
often do not support ECC functionality, leaving SER-sensitive
SRAM users in a difficult situation.
Benefits
• Virtually Zero Soft Error Rate (SER)
Accelerated SER testing has been conducted on 72Mb
ECCRAMs at the LANSCE WNR facility in Los Alamos,
NM. The following table presents the nominal cosmic ray
FIT for each event type (SBU, MCU, SEFI, SEL) for the
tested devices at sea level New York City. FIT rate values
Bringing the ECC on-chip resolves the issue by removing the
burden from the controller, thereby simplifying custom
9
are per Mbit per 10 hours, and represent 95% confidence
rd
controller design and maximizing 3 party controller options
level.
for the application. It also provides utilization efficiency
benefits that are explained further below.
Cosmic Ray FIT Values at Sea Level, New York City
Accordingly, GSI Technology has developed a family of
SigmaQuad™ and SigmaDDR™ SRAMs with on-chip ECC,
referred to collectively as “ECCRAMs”.
1
2
3
4
5
Test
SEU
FIT
SBU
FIT
MCU
FIT
SEF
FIT
SEL
FIT
Condition
ECC
Disabled
567
0
305
0
262
0
0
0
0
0
Implementation
GSI ECCRAMs utilize a single-bit error detection and
correction Hamming Code algorithm. The ECC is implemented
independently on each external 9-bit data bus, across the entire
18-bit DDR data word transmitted on the bus. For example,
x36 devices have four such 9-bit busses, and x18 devices have
two such 9-bit busses.
ECC
Enabled
Notes:
1. SEU = Single-Event Upset (SBU + MCU)
2. SBU = Single-Bit Upset
3. MCU = Multi-Cell Upset
4. SEFI = Single-Event Functional Interrupt
5. SEL = Single-Event Latch-up
Five ECC parity bits (invisible to the user) are utilized per 18
data bits (visible to the user). Consequently, 72Mb ECCRAMs
(for example) are actually 92Mb devices, with 72Mb visible
and available to the user.
With ECC disabled, the total SEU FIT rate was 567,
comprising an SBU FIT rate of 305 and a MCU FIT rate
of 262.
The ECC algorithm neither corrects nor detects multi-bit
errors. However, the ECCRAMs are architected in such a way
that a single SER event very rarely causes a multi-bit error
across any given “data word”, where a “data word” in this
context represents the data transmitted as the result of a single
read or write operation to a particular address.
With ECC enabled, the total SEU FIT rate decreased to 0,
indicating that all SBUs and MCUs that occurred during
the testing were corrected by the ECC. Which indicates
that none of the MCUs that occurred during the testing
Rev: 1.00 11/2012
1/3
© 2012, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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