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AN1020

更新时间： 2024-10-30 17:01:35

品牌	Logo	应用领域
GSI		PC 微控制器静态存储器
页数	文件大小	规格书
10页	242K
描述
Interfacing GSI Sync SRAMs to a Freescale Mutiplexed MPC567xF or PXR40xx Microcontroller

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AN1020

Interfacing GSI Sync SRAMs to a Freescale Multiplexed MPC567xF or PXR40xx Microcontroller

Introduction

This application note will discuss interfacing a Freescale MPC567xF microcontroller or the Freescale e200 PowerA PXR40xx

microcontroller operating in Multiplexed mode with GSI Synchronous Burst SRAMs.

Compatibility

The Freescale MPC567xF and PXR40xx are capable of interfacing with SRAMs that operate in either Flow Through or Pipeline

mode, which is selectable by the addition of wait states in the MPC567xF read timing. The SRAMs must operate in a Late Write

mode, where the data and byte writes are supplied one cycle after the write command is loaded. All of GSI’s Synchronous Burst

SRAMs are compatible with the Freescale MPC567xF and PXR40xx.

Interfacing Using 16-bit Multiplexed Mode

Figure 1 shows the basic connection between either an MPC567xF or PXR40xx and a GSI SRAM. Both microcontrollers have

been configured internally to interface with the SRAM using 16-bit Multiplexed mode. During an address cycle while operating in

16-bit Multiplexed mode, the microcontroller utilizes the Data Bus D_DAT[0:15] and parts of the address D_ADD[8:15] to issues

addresses A[0:23]. The FT pin controls whether the SRAM operates in Pipeline mode or Flow Through mode. This pin needs to be

tied to V if the microcontroller is operating in a zero wait state Read mode, which is also referred to as Flow Through mode in

the SRAM datasheet. The FT pin will need to be tied to V if the microcontroller is operating in a one wait state Read mode,

which is also referred to as Pipeline mode in the SRAM datasheet.

Figure 1: Connection diagram 16-bit Multiplexed mode

Freescale MPC567xF

or PXR40xx

V_DDfor Pipeline mode

GSI Synchronous SRAM

A[16:23]

D_ADD[8:15]

D_DAT[0:15]

DQ[0:15] & A[0:15]

ADSP

V_SSfor Flow Through mode

CLKOUT

RD_WR

CSx

V_DD

ADSC

WE[0:3]

B_A–B_D

BDIP

ADV

LBO

V_SS

The MPC567xF and PXR40xx microcontrollers use a Late Write protocol when performing L2 cache writes. This requires the

design to use the ADSP pin to configure the SRAM to utilize a Late Write protocol.

Rev: 1.01 3/2011

1/10

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...10

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