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AN1017

更新时间： 2024-10-30 17:01:11

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SigmaQuad-IIIe Input and Output Clocking Scheme

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Preliminary

AN1017

SigmaQuad-IIIe Input Clocking Schemes

KD and KD Input Clocks

In previous industry-standard synchronous SRAMs (e.g., Burst SRAMs, NBT™ SRAMs, SigmaQuad/DDR/QDR™ -I/-II/-II+

SRAMs, etc.), all synchronous Address, Control, and Write Data inputs transmitted by the SRAM Controller (henceforth referred

to simply as the “Controller”) to the SRAM at a particular clock phase are latched by a common input clock. In x36 versions of

these SRAMs, that can equate to approximately 60 inputs that are latched by a common input clock.

As operating (clock) frequencies increase, the ability to latch so many synchronous inputs with a common input clock becomes

increasingly more difficult, because any skew (introduced by the Controller and the system board) between the slowest and fastest

synchronous input, with respect to that input clock, becomes an increasingly greater percentage of the cycle time, leaving a

decreasingly lower percentage of the cycle time available for input setup and hold windows. This is especially true in SigmaQuad-

IIIe Burst of 2 devices, because both the Write Data and the Address inputs are Double Data Rate (DDR) (i.e., they are latched

twice per clock cycle, and therefore their ideal valid windows (with zero skew) are only half a clock cycle to begin with).

In order to address this issue, all SigmaQuad-IIIe and SigmaDDR-IIIe SRAMs have two pairs of positive and negative input

clocks, KD0/KD0 and KD1/KD1, which are used to latch synchronous Write Data inputs only. Specifically:

• KD0 latches phase 0 DDR Write Data inputs D/DQ[17:0] in x36 devices (D/DQ[8:0] in x18 devices).

• KD1 latches phase 0 DDR Write Data inputs D/DQ[35:18] in x36 devices (D/DQ[17:9] in x18 devices).

• KD0 latches phase 1 DDR Write Data inputs D/DQ[17:0] in x36 devices (D/DQ[8:0] in x18 devices).

• KD1 latches phase 1 DDR Write Data inputs D/DQ[35:18] in x36 devices (D/DQ[17:9] in x18 devices).

The primary positive and negative input clocks, CK and CK, are used to latch synchronous Address and Control inputs only (CK

latches phase 0 Address and Control inputs; CK latches phase 1 Address inputs—no Control inputs are valid during phase 1 of the

clock cycle, in SigmaQuad-IIIe devices).

By using three input clocks (CK/KD0/KD1 for phase 0 inputs, CK/KD0/KD1 for phase 1 inputs), rather than one input clock, to

latch the synchronous Address, Control, and Write Data inputs at a particular clock phase, the skew between the slowest and fastest

synchronous input, with respect to the input clock used to latch them, can be reduced (the misalignment of 20 signal edges should

be less than the misalignment of 60 signal edges), thereby increasing the size of the valid window and making it easier for the

Controller to meet SRAM input setup and hold times.

Rev: 1.00b 10/2010

1/2

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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