Datasheet > AMD27C64

AMD27C64

更新时间： 2022-11-24 21:54:46

品牌	Logo	应用领域
超微 - AMD		可编程只读存储器电动程控只读存储器
页数	文件大小	规格书
11页	92K
描述
64 Kilobit (8,192 x 8-Bit) CMOS EPROM

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AMD27C64 数据手册

FINAL

Advanced

Micro

Am27C64

64 Kilobit (8,192 x 8-Bit) CMOS EPROM

Devices

DISTINCTIVE CHARACTERISTICS

■ Fast access time

■ Latch-up protected to 100 mA from –1 V to

V_CC+ 1 V

— 45 ns

■ High noise immunity

■ Low power consumption

— 20 µA typical CMOS standby current

■ JEDEC-approved pinout

■ Versatile features for simple interfacing

— Both CMOS and TTL input/output

compatibility

■ Single +5 V power supply

■ ±10% power supply tolerance available

■ 100% Flashrite^TMprogramming

— Typical programming time of 1 second

— Two line control functions

■ Standard 28-pin DIP, PDIP, and 32-pin PLCC

packages

GENERAL DESCRIPTION

The Am27C64 is a 64-Kbit ultraviolet erasable program-

mable read-only memory. It is organized as 8K words by

8 bits per word, operates from a single +5 V supply, has

a static standby mode, and features fast single address

location programming. Products are available in win-

dowed ceramic DIP packages as well as plastic one

time programmable (OTP) PDIP, and PLCC packages.

controls, thus eliminating bus contention in a multiple

bus microprocessor system.

AMD’s CMOS process technology provides high speed,

low power, and high noise immunity. Typical power con-

sumption is only 80 mW in active mode, and 100 µW in

standby mode.

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in blocks,

or at random. The Am27C64 supports AMD’s Flashrite

programming algorithm (100 µs pulses) resulting in a

typical programming time of 1 second.

Typically, any byte can be accessed in less than 45 ns,

allowing operation with high-performance microproces-

sors without any WAIT states. The Am27C64 offers

separate Output Enable (OE) and Chip Enable (CE)

BLOCK DIAGRAM

Data Outputs

DQ0–DQ7

VCC

VSS

VPP

Output Enable

Chip Enable

and

Output

Buffers

Prog Logic

PGM

Decoder

Gating

A0–A12

Address

Inputs

65,538

Bit Cell

Matrix

Decoder

11419D-1

Publication# 11419 Rev. D Amendment/0

Issue Date: May 1995

2-10

12 3 4 5 6 7...11

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